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Interrupt Agent

Concept WIKI v1 · 5/27/2026

An Interrupt Agent is a verification-testbench component used in the Ibex core environment to randomly drive stimulus onto the core’s interrupt pins during test execution.

Interrupt Agent

Definition

In the Ibex core verification testbench, the Interrupt Agent is the component used to drive interrupt stimulus onto the Ibex core. Specifically, it randomly drives stimulus on the core’s interrupt pins while a test is executing.

Role in the Ibex testbench

The Interrupt Agent appears as part of the Ibex testbench architecture alongside other verification components such as memory interface agents and a memory model. While the memory interface agents respond to instruction-fetch and load-store-unit memory requests, the Interrupt Agent provides asynchronous interrupt-pin stimulus to exercise interrupt behavior during execution.

The broader Ibex verification flow stimulates the core to execute a program stored in memory and compares the core trace against a Spike instruction-set-simulator trace. Within this environment, interrupt stimulus is one of the external stimuli used during tests; the test and sequence library includes sequences that drive interrupt and debug stimulus into the core.

Verification context

Interrupt behavior is part of the Ibex verification scope. The cited testplan discussion identifies exception and interrupt testing among the areas required for comprehensive Ibex verification. The co-simulation system can also support interrupt requests: interrupts observed in RTL simulation are forwarded to the ISS so the RTL and ISS remain synchronized.

LINKED ENTITIES

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CITATIONS

4 sources
4 citations
[1] The Interrupt Agent is used to drive random stimulus onto the Ibex core's interrupt pins during test execution. [PDF] UVM based design veri cation of a RISC-V CPU core - POLITesi
[2] The Ibex testbench includes memory interface agents and a memory model, and it stimulates the core to execute a program stored in memory while comparing the core trace against a Spike ISS trace. [PDF] UVM based design veri cation of a RISC-V CPU core - POLITesi
[3] The Ibex test and sequence library includes sequences used to drive interrupt and debug stimulus into the core. [PDF] UVM based design veri cation of a RISC-V CPU core - POLITesi
[4] Exception and interrupt testing are identified as part of the Ibex verification scope, and the co-simulation system supports interrupt requests observed in RTL simulation and forwarded to the ISS. [PDF] UVM based design veri cation of a RISC-V CPU core - POLITesi