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Illegal Instruction Generation

Concept WIKI v1 · 5/25/2026

Illegal Instruction Generation

Overview

Illegal Instruction Generation is a verification capability used to create invalid or unsupported instruction encodings as part of processor validation. In the RISC-V verification ecosystem, this capability is supported by RISCV-DV, an open-source SystemVerilog/UVM instruction generator for RISC-V processor verification.[1]

RISCV-DV can generate both legal and special-case instruction streams, including illegal instructions and HINT instructions, to help verify that a RISC-V processor implementation correctly detects, traps, and handles unsupported or invalid instruction encodings.[1]

Role in RISC-V Verification

Illegal instruction generation is useful for validating architectural exception behavior. A processor must respond correctly when it encounters an instruction that is not valid for the implemented ISA, privilege configuration, or execution context. RISCV-DV includes illegal instruction generation alongside other verification features such as trap and interrupt handling, privileged CSR randomization, page table randomization, and MMU stress testing.[1]

This makes illegal instruction generation part of a broader constrained-random verification flow for RISC-V cores.

Support in RISCV-DV

RISCV-DV is a SystemVerilog/UVM-based open-source instruction generator targeting RISC-V processor verification.[1] It supports illegal instruction and HINT instruction generation as one of its built-in features.[1]

Related supported capabilities include:

  • Random instruction stream generation
  • Illegal instruction and HINT instruction generation
  • Trap and interrupt handling
  • Privileged CSR setup randomization
  • Privileged CSR test suite
  • Page table randomization and exception generation
  • MMU stress-test support
  • Random forward and backward branch instructions
  • Sub-program generation and random program calls
  • Mixing directed instructions with random instruction streams
  • Debug mode support with randomized debug ROM
  • Instruction generation coverage model
  • Co-simulation with multiple instruction set simulators, including Spike, riscv-ovpsim, Whisper, and Sail-RISC-V[1]

Supported ISA and Privilege Modes

RISCV-DV supports illegal instruction generation within a generator that targets the following RISC-V instruction set configurations:

Category Supported Values
ISA variants RV32IMAFDC, RV64IMAFDC
Privilege modes Machine mode, supervisor mode, user mode

These privilege-mode capabilities are important because illegal-instruction behavior may interact with privileged execution, CSR setup, traps, exceptions, and page-table behavior.[1]

Tool and Environment Requirements

To run RISCV-DV, an RTL simulator with SystemVerilog and UVM 1.2 support is required.[1]

The generator has been verified with the following simulators:

  • Synopsys VCS
  • Cadence Incisive/Xcelium
  • Mentor Questa
  • Aldec Riviera-PRO[1]

The EDA tool environment must be properly configured before running the generator.[1]

Getting the Source

RISCV-DV can be obtained from GitHub:

git clone https://github.com/google/riscv-dv.git

This repository contains the generator source, documentation, scripts, and supporting infrastructure.[1]

Running RISCV-DV

RISCV-DV can be run in two main ways.

Developer Workflow

For developers working with multiple repository clones, directly invoking the Python script is recommended:

pip3 install -r requirements.txt
python3 run.py --help

This approach allows developers to work from a specific checkout without relying on an installed package wrapper.[1]

User Workflow

For normal users, installing the repository as an editable Python package is recommended:

export PATH=$HOME/.local/bin/:$PATH
pip3 install --user -e .

After this setup, changes inside the repository are immediately available through the run and cov commands, without repeatedly reinstalling the package.[1]

Verification Integration

Illegal instruction generation in RISCV-DV is designed to integrate with larger verification environments. RISCV-DV supports handshake communication with a testbench and co-simulation with multiple instruction set simulators, including Spike, riscv-ovpsim, Whisper, and Sail-RISC-V.[1]

This enables generated instruction streams, including illegal-instruction cases, to be compared against reference models or used in RTL simulation flows.

Documentation and Customization

RISCV-DV includes documentation under its docs directory. The documentation explains how to set up and customize the generator, and it can be generated using the repository makefile. A prebuilt version is available under:

docs/build/singlehtml/index.html

An HTML preview is also available from the RISCV-DV repository documentation.[1]

Project Status

RISCV-DV has been contributed to CHIPS Alliance, and regular working-group meetings are held to discuss issues, feature priorities, and development progress.[1]

Bug reports, integration issues, and feature requests are handled through the project repository issue tracker.[1]

See Also