Generated C++ ISS

CodeArtifact

Generated C++ ISS is the C++ instruction-set-simulator core produced from an ITL-based complete property suite in the paper “Generating an Efficient Instruction Set Simulator from a Complete Property Suite.” The artifact is derived from the ISA model used for formal verification, so after the equivalence proof it is intended to comply with both the ISA and the verified RTL design.

First seen 5/29/2026

Last seen 5/29/2026

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Overview

Generated C++ ISS refers to the automatically generated C++ instruction set simulator described in Generating an Efficient Instruction Set Simulator from a Complete Property Suite. The simulator is generated from the same complete property suite used for formal processor verification, rather than from a separately hand-written simulator model or an architecture-description-language reimplementation. This addresses a key risk of traditional ISS development: a simulator independently reimplementing the ISA can diverge from the actual design or ISA. [C1]

The paper presents this artifact as a way to obtain a provably correct simulator with relatively small effort. Because the property suite is used in the formal verification of the processor, the generated simulator is constructed from the ISA model that is checked against the RTL design. [C2]

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RELATIONSHIPS

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Generating an Efficient Instruction Set Simulator from a Complete Property Suite ← introduces 100% 3e

The paper presents an approach to automatically generate a C++ instruction set simulator from a complete property suite.

Instruction Set Architecture implements → 100% 2e

The generated C++ ISS implements the ISA as derived from the complete property suite.

Instruction Set Simulator implements → 100% 2e

The generated C++ ISS is an implementation of an instruction set simulator.

Complete Property Suite derived from → 100% 2e

The generated C++ ISS is automatically derived from the complete property suite.

LINKED ENTITIES

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Generating an Efficient Instruction Set Simulator from a Complete Property Suite INTRODUCES Extracted graph relationship

Instruction Set Architecture IMPLEMENTS Extracted graph relationship

Instruction Set Simulator IMPLEMENTS Extracted graph relationship

Complete Property Suite DERIVED_FROM Extracted graph relationship

CITATIONS

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[1] Traditional ISS development often requires a separate ISA reimplementation, creating a risk that the ISS diverges from the design or ISA. Generating an Efficient Instruction Set Simulator from a Complete Property Suite

[2] The paper presents automatic generation of an instruction set simulator from a complete property suite used for formal processor verification, yielding a provably correct simulator with relatively small effort. Generating an Efficient Instruction Set Simulator from a Complete Property Suite

[3] The generated ISS starts from an ITL ISA description in which instruction decoding, architectural state, and a next_state function define instruction execution; next_state forms the core of the ISA. Generating an Efficient Instruction Set Simulator from a Complete Property Suite

[4] A complete property suite uniquely captures design behavior for all state/input combinations and forms a functionally equivalent model of the verified design; designs satisfying all properties of a complete suite are formally equivalent. Generating an Efficient Instruction Set Simulator from a Complete Property Suite

[5] The generated C++ class Sim is the core of the ISS, contains instruction-execution code, holds architectural state, and is used with a wrapper for execution control and peripheral integration. Generating an Efficient Instruction Set Simulator from a Complete Property Suite

[6] The generated ISS can cache decoded instruction information to avoid repeated decoding, which the paper identifies as efficient because software locality such as loops can reduce simulation runtime. Generating an Efficient Instruction Set Simulator from a Complete Property Suite

[7] The ISS can be generated before the full ISA/RTL equivalence proof is completed, but full confidence in compliance with the design is achieved at the end of verification; regeneration is needed when the ISA changes. Generating an Efficient Instruction Set Simulator from a Complete Property Suite

[8] The approach was evaluated by generating an ISS for a small pipelined processor, and the paper reports feasibility for an industrial design with performance comparable to custom state-of-the-art simulators. Generating an Efficient Instruction Set Simulator from a Complete Property Suite