gen_instr function

CodeArtifact

The `gen_instr` function is a RISCV-DV generator routine shown in DVCon proceedings as the implementation used to randomize an initial instruction dump. It configures allowed instructions, randomizes `instr_list` either sequentially or in parallel depending on configuration thresholds, removes trailing branch instructions, and temporarily disables and re-enables garbage collection around the generation work.

First seen 5/25/2026

Last seen 5/25/2026

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Overview

gen_instr is presented in Listing 9, "Parallelizing Randomization of the Initial Instruction Dump," as a function that randomizes the initial instruction list used by the RISCV-DV generator. The function signature shown is:

void gen_instr(bool no_branch = false,
               bool no_load_store = true,
               bool is_debug_program = false)

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riscv-dv part of → 100% 2e

The gen_instr function is part of the RISCV-DV generator.

CITATIONS

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9 citations — click to expand

[1] The `gen_instr` function is shown as Listing 9, titled "Parallelizing Randomization of the Initial Instruction Dump," with parameters `no_branch`, `no_load_store`, and `is_debug_program`. [PDF] Crafting a Million Instructions/Sec RISCV-DV - DVCon Proceedings

[2] `gen_instr` disables garbage collection, sets up allowed instructions, asserts a non-empty `instr_list`, and randomizes instructions. [PDF] Crafting a Million Instructions/Sec RISCV-DV - DVCon Proceedings

[3] `gen_instr` uses a sequential path when `instr_list.length <= cfg.par_instr_threshold` or `cfg.par_num_threads == 1`, calling `randomize_instr(instr, is_debug_program)` for each instruction. [PDF] Crafting a Million Instructions/Sec RISCV-DV - DVCon Proceedings

[4] When parallelized, `gen_instr` divides `instr_list` across `cfg.par_num_threads`, creates forked workers, randomizes `instr_list[i]` in each worker, assigns thread affinity, appends forks to a list, and joins them. [PDF] Crafting a Million Instructions/Sec RISCV-DV - DVCon Proceedings

[5] `gen_instr` removes trailing branch instructions because a final branch instruction would have no forward branch target, then re-enables garbage collection. [PDF] Crafting a Million Instructions/Sec RISCV-DV - DVCon Proceedings

[6] RISCV-DV profiling identified non-directed instruction-stream dumping into main-program and sub-program instruction lists as a major bottleneck, with most effort spent on randomization and constraint solving. [PDF] Crafting a Million Instructions/Sec RISCV-DV - DVCon Proceedings

[7] The paper describes the first two RISCV-DV bottlenecks as linear in algorithmic complexity and suitable for multicore parallelization. [PDF] Crafting a Million Instructions/Sec RISCV-DV - DVCon Proceedings

[8] RISCV-DV execution time varies significantly with user-selected parameters, and the profiling example used `riscv_instr_base_test` with seven directed streams covering RISC-V instruction categories. [PDF] Crafting a Million Instructions/Sec RISCV-DV - DVCon Proceedings

[9] The paper shows `uvm_trace` calls around instruction generation with the `GEN INSTR` tag and explains that `uvm_trace` provides macro-level profiling but incurs an operating-system call to fetch current clock time. [PDF] Crafting a Million Instructions/Sec RISCV-DV - DVCon Proceedings