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DEC Alpha 21264

Concept WIKI v1 · 5/26/2026

The DEC Alpha 21264 Microprocessor is identified in the provided evidence as a multiple-issue, out-of-order, superscalar Alpha processor. A cited 1998 DAC paper focused on its functional verification.

Overview

The DEC Alpha 21264 Microprocessor is described in the available evidence as a multiple-issue, out-of-order, superscalar Alpha processor.

Functional verification reference

The provided source cites a paper by S. Taylor et al. titled “Functional Verification of a Multiple-Issue, Out-of-Order, Superscalar Alpha Processor—the DEC Alpha 21264 Microprocessor.” The paper appeared in the Proceedings of the 35th Design Automation Conference, identified as DAC 98, published by ACM Press in 1998, on pages 638–643.

Evidence scope

The available evidence is bibliographic. It supports the processor characterization above and the existence of a functional-verification publication about the DEC Alpha 21264, but it does not provide additional implementation details, performance data, instruction-set details, or design specifications.

CITATIONS

4 sources
4 citations
[1] The DEC Alpha 21264 Microprocessor is described as a multiple-issue, out-of-order, superscalar Alpha processor. [PDF] Genesys-pro: innovations in test program generation for functional ...
[2] S. Taylor et al. authored a paper titled “Functional Verification of a Multiple-Issue, Out-of-Order, Superscalar Alpha Processor—the DEC Alpha 21264 Microprocessor.” [PDF] Genesys-pro: innovations in test program generation for functional ...
[3] The functional-verification paper appeared in the Proceedings of the 35th Design Automation Conference (DAC 98), ACM Press, 1998, pages 638–643. [PDF] Genesys-pro: innovations in test program generation for functional ...
[4] The available evidence is bibliographic and does not provide implementation details, performance data, instruction-set details, or design specifications. [PDF] Genesys-pro: innovations in test program generation for functional ...