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Debug Mode Support

Concept WIKI v1 · 5/25/2026

**Debug Mode Support** is a feature of **RISCV-DV**, an open-source SystemVerilog/UVM instruction generator used for RISC-V processor verification. RISCV-DV includes support for debug-mode-oriented test generation through a **fully randomized debug ROM**, enabling randomized verification scenarios that exercise debug-related processor behavior as part of generated instruction streams.[^ff810966]

Debug Mode Support

Debug Mode Support is a feature of RISCV-DV, an open-source SystemVerilog/UVM instruction generator used for RISC-V processor verification. RISCV-DV includes support for debug-mode-oriented test generation through a fully randomized debug ROM, enabling randomized verification scenarios that exercise debug-related processor behavior as part of generated instruction streams.[1]

Context

RISCV-DV is a SystemVerilog/UVM-based open-source instruction generator for RISC-V processor verification.[1] It supports the RV32IMAFDC and RV64IMAFDC instruction sets, as well as machine, supervisor, and user privileged modes.[1] Within this broader verification environment, debug mode support is listed as one of the generator’s supported features.[1]

Feature Summary

RISCV-DV’s debug mode support includes:

  • Debug mode support as part of the instruction-generation feature set.[1]
  • A fully randomized debug ROM, allowing the debug ROM contents or behavior used by the generator flow to be randomized during verification.[1]
  • Integration alongside other randomized and privileged-mode verification capabilities, such as privileged CSR setup randomization, trap/interrupt handling, page-table randomization, and illegal-instruction generation.[1]

Role in Verification

In a RISC-V verification flow, debug mode support helps expand test coverage beyond ordinary instruction execution. Since RISCV-DV can generate randomized programs and privileged-mode scenarios, its debug mode capability can be used together with other stress features such as trap and interrupt handling, CSR randomization, and random branches to create more diverse processor verification workloads.[1]

Related RISCV-DV Capabilities

Debug mode support is one feature within RISCV-DV’s broader verification feature set. Other supported capabilities include:

  • Page-table randomization and exception generation.[1]
  • Privileged CSR setup randomization and a privileged CSR test suite.[1]
  • Trap and interrupt handling.[1]
  • MMU stress-test generation.[1]
  • Sub-program generation and random program calls.[1]
  • Illegal instruction and HINT instruction generation.[1]
  • Random forward and backward branch instruction generation.[1]
  • Mixing directed instructions with random instruction streams.[1]
  • Instruction-generation coverage modeling.[1]
  • Co-simulation with multiple instruction-set simulators, including Spike, riscv-ovpsim, Whisper, and Sail RISC-V.[1]

Tool and Environment Requirements

To use RISCV-DV, including its debug mode support, an RTL simulator with SystemVerilog and UVM 1.2 support is required.[1] The generator has been verified with Synopsys VCS, Cadence Incisive/Xcelium, Mentor Questa, and Aldec Riviera-PRO simulators.[1]

Source Availability

RISCV-DV can be obtained from its public GitHub repository:

git clone https://github.com/google/riscv-dv.git

The project can be run directly with Python scripts for development workflows or installed as a Python package for normal use.[1]

References

[1]: RISCV-DV project evidence, feature list and usage notes, including “Debug mode support, with fully randomized debug ROM.”