Cycle-Approximate Simulator
A Cycle-Approximate Simulator is presented in OpenVADL materials as an output or target in the OpenVADL tool flow. In the overview diagram, a VADL specification is processed by the VADL frontend into the VIAM intermediate representation, with architecture synthesis leading toward a cycle-approximate simulator; the same overview also shows QEMU simulation and hardware as other generated artifacts or targets.[1]
Relationship to OpenVADL
The available evidence positions the Cycle-Approximate Simulator concept within the OpenVADL ecosystem rather than as a fully specified standalone tool. The OpenVADL QEMU-generation slides list “Cycle Approximate Simulator based on the ISS” under future work, indicating that the simulator was planned to build on the instruction-set simulator work.[2]
Status from the provided evidence
The evidence does not provide implementation details, timing-model semantics, supported architectures, or an API for the Cycle-Approximate Simulator. It supports only that:
- it appears in the OpenVADL overview flow as a simulator target related to VIAM and architecture synthesis;[1]
- it is identified as future work based on the ISS.[2]
References
[1] Zottele et al., “Generation of a QEMU-Based Instruction Set Simulator from a Processor Description in OpenVADL,” OpenVADL Overview slide.
[2] Zottele et al., “Generation of a QEMU-Based Instruction Set Simulator from a Processor Description in OpenVADL,” Conclusion & Future Work slide.