Skip to content
STIMSMITH

Coverage Closure

Concept WIKI v2 · 5/30/2026

Coverage Closure is the hardware verification process of reaching sufficient functional and code coverage to justify confidence that relevant design behaviours have been tested. The provided evidence emphasizes feedback-driven simulation techniques—supervised test selection, multi-armed-bandit scheduling, feedback-based sequence-duration control, and recurrent-neural-network constraint tuning—that use coverage feedback to prioritize stimuli and accelerate functional coverage convergence.

Definition

Coverage Closure is the process of achieving sufficient functional and code coverage to provide confidence that all relevant design behaviours have been tested. [Coverage closure definition]

In simulation-based processor verification, stimuli are generated and applied to a design while achieved functional coverage is monitored as an indicator of verification completeness. [Simulation-based coverage monitoring]

Why closure is difficult

Constrained-random test generation is widely used because randomness creates test diversity, but random tests can repeatedly exercise the same design logic. As verification progresses, many constrained-random tests may add little or no new functional coverage, and constraints are often manually written to steer generation toward interesting, hard-to-reach, or untested logic. [Constrained-random limitations]

This makes coverage closure an optimization problem as well as a measurement problem: verification teams need not only to measure uncovered behavior, but also to choose tests, constraints, or sequence durations that are likely to increase coverage efficiently. [Constrained-random limitations]

Coverage-directed test selection

The paper Supervised Learning for Coverage-Directed Test Selection in Simulation-Based Verification introduces coverage-directed test selection, a supervised-learning method that learns from coverage feedback. The method randomly generates many tests, selects an effective subset, and prioritizes tests that have a high probability of increasing functional coverage before simulation. [Supervised coverage-directed selection]

According to the paper abstract, this approach can reduce manual constraint writing, prioritize effective tests, reduce verification resource consumption, and accelerate coverage closure on a large industrial hardware design. [Supervised coverage-directed selection]

Multi-armed bandits for autonomous closure

Another evidence source applies the Multi-Armed Bandit (MAB) model to UVM verification with the goal of reaching coverage goals faster than traditional approaches. In the MAB formulation, test sequences are treated as the available “arms”; each sequence is run for a number of cycles, a reward is computed from its coverage performance against selected properties, and the policy chooses the next sequence using an exploration/exploitation trade-off. [MAB formulation]

The same source states that verification engineers define functional coverpoints describing architecturally interesting aspects of the design under test. The achieved coverage of those properties provides a quantitative measure of the effectiveness of the test plan and of the ability of the test sequences to explore general and corner-case behavior. [Functional coverpoints]

In RISC-V case studies, the MAB framework was used for unit-level testing of an instruction-fetch stage and top-level testing of a 2-way superscalar out-of-order RISC-V processor. The reported result was that higher functional coverage goals were reached without manual intervention and with simulation-time savings between 1.5× and 2× compared with random scheduling of available tests. [MAB RISC-V case studies]

A more detailed UCB1 experiment used the same 40 virtual sequences for random scheduling and MAB scheduling. Random application for 5,000 trials reached between 82% and 91% coverage depending on seed, while the MAB framework reached the same coverage faster; the table reports an average of 1,988 MAB trials versus 5,000 random trials, corresponding to a 60% average saving. [UCB1 trial reduction]

The evidence also notes a limitation: when both random scheduling and UCB1 use the same fixed set of 40 virtual sequences, UCB1 does not improve the inherent quality of that sequence set; rather, it identifies the set’s coverage potential more quickly than traditional approaches. [UCB1 sequence-set limitation]

Other feedback-driven techniques

A separate feedback-based technique autonomously adjusts the simulation duration of each test sequence during a verification campaign. It uses each sequence’s incremental contribution to functional coverage to decide how long that sequence should run in the next simulation round, and the reported results include approximately 70% simulation-time savings for different sets of test sequences. [Feedback-based duration control]

Another paper proposes dynamically altering constraints for pseudorandom generators using a recurrent neural network that receives coverage feedback from simulation. Its abstract reports that coverage closure is achieved much sooner and that the method can isolate a small set of high-coverage stimuli suitable for regression tests. [RNN constraint tuning]

Practical closure loop supported by the evidence

A coverage-closure workflow supported by the evidence can be summarized as:

  1. Define functional coverpoints and coverage goals for architecturally interesting behavior. [Functional coverpoints]
  2. Generate or preselect constrained-random, directed, or parameterized test sequences. [MAB formulation]
  3. Simulate tests and collect coverage feedback. [Simulation-based coverage monitoring]
  4. Use feedback to select tests, schedule sequences, tune constraints, or adjust sequence duration. [Supervised coverage-directed selection] [MAB formulation] [Feedback-based duration control] [RNN constraint tuning]
  5. Repeat until the achieved functional and code coverage is sufficient to support confidence in the tested behaviours. [Coverage closure definition]

LINKED ENTITIES

1 links
Supervised Learning for Coverage-Directed Test Selection in Simulation-Based Verification EVALUATES

CITATIONS

11 sources
11 citations
[1] Coverage closure is the process of achieving sufficient functional and code coverage to provide confidence that all relevant design behaviours have been tested. RISC-V test generation: random, directed, coverage
[2] Simulation-based processor verification applies generated stimuli and monitors achieved functional coverage to determine verification completeness. Automation of Processor Verification Using Recurrent Neural Networks
[3] Constrained-random generation is widely used, but tests can repeatedly exercise the same design logic; manual constraints are used to bias generation, and late-stage random tests often add little functional coverage. Supervised Learning for Coverage-Directed Test Selection in Simulation-Based Verification
[4] Coverage-directed test selection uses supervised learning from coverage feedback to select and prioritize tests likely to increase functional coverage, reducing manual constraint writing, resource consumption, and closure time. Supervised Learning for Coverage-Directed Test Selection in Simulation-Based Verification
[5] In the MAB formulation for UVM verification, test sequences are treated as arms, rewards are based on coverage performance, and sequence choice balances exploration and exploitation. UVM-based verification of RISC-V superscalar processors
[6] Functional coverpoints describe architecturally interesting aspects of the DUT, and achieved coverage measures test-plan effectiveness and exploration of general and corner cases. UVM-based verification of RISC-V superscalar processors
[7] RISC-V MAB case studies reached higher functional coverage goals without manual intervention and achieved 1.5× to 2× simulation-time savings compared with random scheduling. UVM-based verification of RISC-V superscalar processors
[8] A UCB1 MAB experiment with 40 virtual sequences reached the same coverage as 5,000 random trials faster, averaging 1,988 MAB trials and 60% savings; random coverage ranged from 82% to 91%. UVM-based verification of RISC-V superscalar processors
[9] With a fixed sequence set, UCB1 does not improve the sequence set’s quality; it identifies the set’s coverage potential more quickly than traditional approaches. UVM-based verification of RISC-V superscalar processors
[10] A feedback-based technique adjusts sequence simulation duration using incremental functional-coverage contribution and reports approximately 70% simulation-time savings. UVM-based verification of RISC-V superscalar processors
[11] A recurrent-neural-network technique dynamically alters pseudorandom-generator constraints using coverage feedback, achieving coverage closure sooner and isolating a small set of high-coverage regression stimuli. Automation of Processor Verification Using Recurrent Neural Networks

VERSION HISTORY

v2 · 5/30/2026 · gpt-5.5 (current)
v1 · 5/25/2026 · gpt-5.5