Definition

A constrained-random scenario is a test stimulus scenario that uses randomization while applying explicit constraints to the generated items. In the microprocessor-verification example, a constrained-random scenario can focus a long instruction sequence on arithmetic operations by constraining all operations to the computational kind and excluding branches, loads, and stores.

Role in stimulus generation

Constrained-random scenarios are one of three scenario types described for processor stimulus generation:

• Constrained-random scenarios: randomize stimulus within constraints.
• Directed-random scenarios: combine directed setup with random instruction streams.
• Directed scenarios: cover specific functionality, including scenarios loaded from a pre-assembled program trace.

A scenario generator can work with any of these three types. Given a set of scenario objects, it randomly selects and randomizes one scenario, repeating until a user-specified condition is reached.

SystemVerilog representation

The source describes controlling both test scenarios and the scenario-generator component so that stimuli can be generated with varying levels of randomness. In the example implementation, instruction items are represented as a dynamic array of instruction objects, and SystemVerilog foreach array constraints are used to specify scenario-related constraints.

Example constraint intent

For a long arithmetic-focused sequence, the scenario can constrain operations to computational instructions only, avoiding branches, loads, and stores.