Definition
Bottom-up generation refers to a code-synthesis strategy in which a program or hardware-design source file is built in two phases:
- Skeleton construction – First, a syntactically valid but incomplete template (skeleton) of the target language is produced via a probabilistic grammar.
- Skeleton completion – Second, the skeleton is completed by inferring identifiers, types, and additional code, yielding a full source-level artifact.
This stands in contrast to top-down generation, where generation begins from a small valid kernel of syntax and the program is incrementally expanded outward while preserving semantic validity at every step.
Origin and Instantiation
The term bottom-up generation as a named technique is introduced in the paper "Bottom-Up Generation of Verilog Designs for Testing EDA Tools" (arXiv:2504.06295v1), which presents the open-source fuzzer ChiGen as its canonical realization.
In ChiGen, bottom-up generation is operationalized through three components:
- Probabilistic grammars in which probabilities are assigned to sequences of production rules (modeled as k-grams), not to sequences of tokens. This governs how skeletons are sampled.
- Type inference using the Hindley-Milner algorithm to assign names and types to the placeholder slots in the skeleton.
- Code injection (referred to in the paper as "Li-Zhendong-style" injection) enabled by data-flow analysis, which fills in module bodies, expressions, and inter-statement dependencies.
Why a Bottom-Up Strategy?
The authors of the ChiGen paper argue that top-down Verilog fuzzers (e.g., Verismith, TransFuzz, VlogHammer) impose a requirement that every intermediate expansion remains semantically valid. This constraint limits the diversity of generated test cases and causes top-down fuzzers to cover fewer than 40% of the production rules of the Verilog-2005 (IEEE 1364-2005) grammar. Because the goal of fuzzing is to expose unexpected behaviors in tools under test — not to produce meaningful hardware — semantically invalid designs are just as useful as valid ones. Bottom-up generation deliberately relaxes the per-step validity requirement by separating skeleton creation from skeleton completion.
Applications
- EDA tool fuzzing. ChiGen uses bottom-up generation to stress-test tools such as Verible, Verilator, and Yosys, and was originally developed to test Cadence's Jasper Formal Verification Platform. It has reportedly found zero-day bugs in these tools.
- Benchmark synthesis. Because the process is generative rather than curated, bottom-up generation can augment existing static HDL benchmark collections (which are limited in size and increasingly needed for training large language models for Verilog) with newly generated samples on demand.
- Other languages. The ChiGen authors hypothesize that the same combination — probabilistic grammars + Hindley-Milner inference + Li-Zhendong code injection — can automate code generation for any programming language, not just Verilog.
Comparison with Related Approaches
| Approach | Starting point | Validity constraint | Example tools |
|---|---|---|---|
| Top-down generation | Minimal valid core | Every expansion is semantically valid | Verismith, TransFuzz, VlogHammer |
| Bottom-up generation | Skeleton + completion | Skeleton syntactically valid; output may be semantically invalid | ChiGen |
| LLM-based generation | Token sequence learned from corpora | Validity is emergent, not enforced | Various Verilog LLMs |
Empirical Properties
- Validity rate. With a lower bound of 500 tokens and a probabilistic context of length two or three, ChiGen produces roughly 30–40% semantically valid designs; with context length one the rate drops further because syntactic constraints are weakened.
- Diversity and coverage. Bottom-up generation outperforms top-down Verilog fuzzers on structural diversity, code coverage, and bug-finding ability in the reported evaluation.
- Modularity. Unlike Verismith (which, in the authors' paraphrase, "generates a set of Verilog modules one line at a time, making decisions locally"), bottom-up generation performs the entire generation as a single, more global, modular step.
See Also
- ChiGen — the open-source Verilog fuzzer that implements this technique.
- Hindley–Milner type inference
- Probabilistic context-free grammar
- Li–Zhendong code injection (data-flow-based code completion)
References
- J. V. A. Vieira et al., "Bottom-Up Generation of Verilog Designs for Testing EDA Tools," arXiv:2504.06295v1, April 2025.
- IEEE Std 1364-2005, Verilog Hardware Description Language.