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Bit-flip Fault Effect

Concept WIKI v1 · 7/6/2026

In the µArchiFI microarchitectural fault injection framework, a bit-flip is one of the possible register-level fault effects E within the formal fault model (L, T, E) used to describe an attacker's perturbation of a hardware transition system. It replaces a register's normal update transition with a faulty transition that flips one or more bits of the next-state value while remaining in the same data domain, and is the natural modeling choice for spatially and temporally precise attacks such as laser fault injection.

Bit-flip Fault Effect

In the µArchiFI framework for formal modeling and verification of microarchitectural fault injections (Tollec et al., 2023), the bit-flip fault effect is one of the concrete values that the fault-effect set E ⊂ {set, reset, flips, …} can take when instantiating the fault model (L, T, E) of an attacker.

Role in the Fault Model

The fault model is a triplet:

  • L — the set of possible locations (registers targeted by the fault), with L ⊆ {r1, …, rn}.
  • T ⊂ N — the timing range specifying when, between states si and si+1, the fault may be injected.
  • E — the set of possible effects of the fault, expressed as functions that modify how a register is updated in the next state.

A fault e ∈ E injected in register rj replaces the normal transition function δr_j with a faulty transition δe_j within the same output data type — i.e., the faulty transition is constrained to the same domain as the original register update. Bit-flip is one such in-domain mutation: it flips one or more bits of the register's next-state value rather than overwriting the whole register with a constant (as set/reset would).

Practical Instantiation

The choice of fault effect is guided by the physical accuracy of the underlying injection technique:

  • Laser fault injections are accurate in space and time and are modeled with one or two bit-flip effects.
  • Voltage or clock glitches are less accurate and can affect the whole design, and are therefore modeled with multiple bit-set and bit-reset effects.

Thus the bit-flip effect is the canonical way to capture precise, localized perturbations of a register's stored value.

Use in the Faulty Transition System

The attacker model (L, T, E) and a fault budget N together with an attacker's goal φ (a reachability property on the transition system) define the faulty transition system MF = (S, S0, X, T). For each targeted register rl ∈ L, an additional input xl is introduced that decides whether the next-state value is computed via the normal transition δr_l or via the faulty transition δe_l:

rl' = δe_l(s)  if xl = False
      δr_l(s)  if xl = True

A counter cnt ∈ [[0, N]] bounds the number of fault injections that may be applied along an execution path; the BMC-based verifier (Algorithm 1 in µArchiFI) searches for a path that satisfies φ(sk) while respecting cnt ≤ N. A bit-flip fault effect is the specific δe_l chosen when e = flips (or an equivalent single/multi-bit flip variant) belongs to E.

Relationship to the Attacker Model

The bit-flip effect has no meaning outside an attacker model: it is one of the building blocks with which an adversary parametrizes how registers can be perturbed. Choosing bit-flip over bit-set/reset is a modeling decision that encodes the assumed precision of the physical fault injection means available to the attacker.

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CITATIONS

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[1] The fault effect E ⊂ {set, reset, flips, …} is a set of functions that modifies how a register is updated in the next state, with a fault e ∈ E replacing the transition function δr_j with the faulty transition δe_j within the same data domain. µArchiFI: Formal Modeling and Verification Strategies for Microarchitectural Fault Injections
[2] The fault model is parametrized by the triplet (L, T, E), where L is the set of possible fault locations (registers targeted), T is the timing range, and E is the set of possible fault effects on the system. µArchiFI: Formal Modeling and Verification Strategies for Microarchitectural Fault Injections
[3] Laser fault injections are accurate in space and time and are modeled with only one or two bit-flip effects, while voltage or clock glitches are modeled with multiple bit-set and bit-reset effects. µArchiFI: Formal Modeling and Verification Strategies for Microarchitectural Fault Injections
[4] For each targeted register rl in L, a new input xl is added to control the fault injection; rl' equals the faulty transition δe_l(s) when xl = False and the normal transition δr_l(s) when xl = True. µArchiFI: Formal Modeling and Verification Strategies for Microarchitectural Fault Injections