Overview

The Bedrock coherence protocol is an open-source cache coherence protocol designed for modern shared-memory multicore processors. It was developed and analyzed as part of a research effort revisiting programmable cache coherence engines, and is realized within the BlackParrot 64-bit RISC-V multicore processor.

Protocol Design

Bedrock employs the canonical MOESIF coherence states (Modified, Owned, Exclusive, Shared, Invalid, Forward) as its stable state set. A defining design choice is the elimination of transient coherence states from the protocol, which reduces:

• Implementation burden for coherence engines,
• Concurrency in the protocol's reachable state space, and
• Verification effort required to establish correctness.

The protocol's design complexity, concurrency, and verification requirements have been analyzed and compared against a canonical directory-based invalidate coherence protocol.

System Architecture (BedRock)

A BedRock coherence system is composed of three principal components:

1. Coherence network – an interconnect that transports coherence messages between endpoints.
2. Local Cache Engines (LCEs) – cache controllers that manage coherence transactions for a single instruction or data L1 cache. An LCE interfaces on one side with its L1 cache and on the other with the BedRock coherence network, issuing requests on cache misses and responding to coherence update commands received from the network.
3. Cache Coherence Engines (CCEs) – coherence directories responsible for maintaining coherence for independent subsets of the memory address space. CCEs operate as programmable microcode engines executing both RISC-style general-purpose operations and coherence-specialized operations aimed at accelerating common cache coherence operations, with most instructions completing in a single cycle.

CCE Microarchitecture

The CCE pipeline consists of:

• A fetch stage for instruction decoding, branch prediction, and redirections.
• An execute stage that handles all instruction execution and branch resolution.

The CCE provides:

• 8 general-purpose 64-bit registers,
• A Miss Status Handling Register (MSHR) to track the status of the current outstanding request,
• Coherence network ports for transmitting and receiving messages on the BedRock network,
• Dedicated coherence directory storage,
• Speculative memory access tracking storage, and
• Pending-bit storage.

BlackParrot-BedRock (BP-BedRock) Implementations

Within BlackParrot, the protocol is delivered as three separate cache coherence directory implementations, collectively called BlackParrot-BedRock (BP-BedRock):

1. Fixed-function coherence directory engine – a baseline design that provides a reference point for performance and area comparisons.
2. Microcode-programmable coherence directory – demonstrates the feasibility of implementing a programmable coherence engine capable of maintaining sufficient protocol processing performance.
3. Hybrid fixed-function and programmable coherence directory – blends the protocol processing performance of the fixed-function design with the programmable flexibility of the microcode-programmable design.

Together, the BedRock protocol and its three BP-BedRock implementations demonstrate the feasibility and challenges of including programmable logic within the coherence system of modern shared-memory multicore processors, and pave the way for future research into application- and system-level benefits of programmable coherence engines.

Integration in BlackParrot

The BlackParrot Memory End (ME) implements the Bedrock protocol to provide cache coherence between processor cores, coherent accelerators, and the memory system. This positions Bedrock as the coherence substrate that ties together the core, accelerators, and memory hierarchy within BlackParrot.