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Automatic Test Pattern Generation

Concept WIKI v1 · 7/1/2026

Automatic Test Pattern Generation (ATPG) is an electronic design automation methodology that algorithmically produces input stimulus (test patterns) used to detect faults in digital hardware. It is applied across classical integrated circuits, system-on-chip (SoC) verification flows, and emerging quantum circuit testing, with contemporary approaches using differentiable continuous optimization and stabilizer-based decompositions to scale to large designs and improve fault coverage.

Overview

Automatic Test Pattern Generation (ATPG) refers to the automated construction of input stimulus sequences (test patterns) that, when applied to a device under test, exercise specific faults and produce distinguishable responses. ATPG is a foundational activity in manufacturing test and design verification: as modern integrated circuits grow in complexity, the volume of patterns required to achieve fault coverage has grown accordingly, and a large share of generated patterns is typically concentrated on a small subset of hard-to-detect (HTD) faults.

Classical IC ATPG and the DEFT Approach

Recent research has reformulated the discrete ATPG problem as a continuous optimization task. DEFT (Differentiable Automatic Test Pattern Generation) introduces a mathematically grounded reparameterization that aligns a continuous objective with discrete fault-detection semantics, enabling reliable gradient-based pattern generation. To remain scalable and stable on deep circuit graphs, DEFT integrates a custom CUDA kernel for forward-backward propagation and applies gradient normalization to mitigate vanishing gradients. On a wide range of benchmarks, DEFT reduced pattern count by 27.3% on average and up to 75.9% compared with a leading commercial tool. It also supports practical ATPG settings such as partial assignment pattern generation, producing patterns with 19.3% fewer 0/1 bits while still detecting 35% more faults, positioning it as a complement to existing heuristic engines.

Quantum Circuit ATPG

ATPG has been extended to the testing of logical quantum circuits, where the testing process itself must contend with the inexactness and unreliability of quantum operations. A robust quantum ATPG framework introduces the stabilizer projector decomposition (SPD) for representing quantum test patterns, and constructs test application (state preparation and measurement) using Clifford-only circuits that are efficient and robust for fault-tolerant quantum computation. Because the number of stabilizer projectors grows exponentially in general, an SPD generation algorithm is paired with acceleration techniques that exploit locality and sparsity. The approach is validated through theoretical guarantees under reasonable conditions and through experiments on benchmarks such as Quantum Fourier Transform (QFT), Quantum Volume (QV), and Bernstein–Vazirani (BV) implemented in IBM Qiskit.

ATPG in SoC Verification and Coverage Closure

In system-on-chip verification flows, automated test pattern generation is used to drive random stimulus toward functional coverage closure. Practical SoC environments combine randomized stimulus generation (with weighted control over transaction counts, sizes, masters, read/write/snoopable types, and inter-transaction delays), protocol-specific drivers derived from a generic stimulus base class (for example, AXI), and parameter files such as parameters.txt that supply slave weightage, read/write weightage, and maximum transaction size. Coverage monitors, system-level scenarios, and integrated exclude lists with coverage dumping are used to track progress, while dynamically changing transaction parameters allows each master's stimulus to be regenerated automatically and improves the likelihood of reaching uncovered functional points. Targeted bug-hunting scenarios for SoCs include multi-master access to a single slave (to validate arbitration and response ordering), single-master access to multiple slaves with randomized AXI IDs (to validate out-of-order and ordered transaction handling via reflected BID/RID values), and similar stress configurations.

Outlook

ATPG research continues to broaden along two axes: improving classical ATPG engines for HTD faults at industrial scale through differentiable and gradient-based methods, and adapting the ATPG abstraction to quantum hardware using stabilizer-based representations and Clifford-only test application. Both directions emphasize scalability, stability on deep graph structures, and alignment between the underlying mathematical formulation and the discrete semantics of fault detection.

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CITATIONS

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11 citations
[1] Modern IC complexity drives test pattern growth, with most patterns targeting a small set of hard-to-detect (HTD) faults, motivating new ATPG algorithms for HTD faults. DEFT: Differentiable Automatic Test Pattern Generation
[2] DEFT reformulates the discrete ATPG problem as a continuous optimization task via a mathematically grounded reparameterization aligning the continuous objective with discrete fault-detection semantics, enabling gradient-based pattern generation. DEFT: Differentiable Automatic Test Pattern Generation
[3] DEFT integrates a custom CUDA kernel for forward-backward propagation on deep circuit graphs and applies gradient normalization to mitigate vanishing gradients. DEFT: Differentiable Automatic Test Pattern Generation
[4] Compared with a leading commercial tool on a wide range of benchmarks, DEFT reduced pattern count by 27.3% on average and up to 75.9%. DEFT: Differentiable Automatic Test Pattern Generation
[5] DEFT supports partial assignment pattern generation, producing patterns with 19.3% fewer 0/1 bits while detecting 35% more faults. DEFT: Differentiable Automatic Test Pattern Generation
[6] A quantum ATPG framework represents quantum test patterns via stabilizer projector decomposition (SPD) and uses Clifford-only circuits for test application, which are robust and efficient for fault-tolerant quantum computation. Automatic Test Pattern Generation for Robust Quantum Circuit Testing
[7] An SPD generation algorithm is developed together with acceleration techniques exploiting locality and sparsity, validated theoretically under reasonable conditions and empirically on QFT, QV, and BV benchmarks in IBM Qiskit. Automatic Test Pattern Generation for Robust Quantum Circuit Testing
[8] In SoC verification, automated test pattern generation can be achieved by dynamically changing transaction parameters through a file such as parameters.txt, which specifies slave weightage, read/write weightage, and maximum transaction size, allowing per-master stimulus to be regenerated automatically. Bug hunting SoC designs to achieve full functional coverage closure
[9] SoC random stimulus generation uses weighted control over transaction counts and sizes per master, randomized inter-transaction delays, and type-weighted (read/write/snoopable) transactions, with coverage monitors and integrated exclude lists driving functional coverage closure. Bug hunting SoC designs to achieve full functional coverage closure
[10] Protocol-specific stimulus (for example, AXI) is derived from a generic stimulus base class, with each master mapped to a protocol-specific driver (driver_Master_N) that issues traffic to the DUT. Bug hunting SoC designs to achieve full functional coverage closure
[11] SoC bug-hunting scenarios exercised via generated test patterns include multi-master concurrent access to a single slave (to check arbitration and ordered read/write responses) and a single master issuing transactions to multiple slaves with randomized AXI IDs (to check out-of-order behavior and reflected BID/RID responses). Bug hunting SoC designs to achieve full functional coverage closure