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Automatic Test Generation

Concept WIKI v1 · 7/9/2026

Automatic test generation (ATG) is the automated synthesis of test cases or test programs to verify software and hardware systems. It is applied across software quality assurance (where it helps detect data inconsistency bugs, compatibility issues, and security vulnerabilities) and hardware design verification (where it produces stimuli for simulation-based functional verification of processors and integrated circuits). Recent advances leverage large language models and multi-agent pipelines, while classical approaches employ evolutionary search, genetic algorithms, Bayesian networks, and integer linear programming.

Automatic Test Generation

Automatic test generation (ATG) refers to the automated construction of test inputs, test cases, or test programs used to validate the correctness of software systems or hardware designs. Because manually authored tests are costly and rarely exhaustive, ATG techniques have been developed across multiple domains including software engineering, hardware design verification, and automated program repair.

Software Quality Assurance

In software engineering, ATG is treated as a fundamental quality assurance mechanism. Without effective ATG, developers risk introducing subtle data inconsistency bugs, compatibility issues, and security vulnerabilities that can affect large numbers of end users and cause severe financial losses.

Recent research has explored the use of large language models (LLMs) for software ATG. General-purpose LLM-based methods such as TitanFuzz and YanHui have shown potential, but lack specialization for particular application domains. To address this, a multi-agent ATG system called JsonATG has been proposed for Java JSON libraries (JJLs). JsonATG uses historical bug information as seeds and introduces a code summarization agent and a test validation agent into the generation pipeline. It applies agent-generated program mutation rules tailored to the structural and semantic characteristics of JJLs, such as data streaming operations, serialization formats, and data-binding patterns, and refines the generated tests through post-processing to ensure syntactic and semantic correctness. In experiments, JsonATG achieved higher coverage than two state-of-the-art LLM-based test generation methods on a widely used JSON library, and with a $25 budget reported 59 bugs in fastjson (including non-crashing functional bugs), of which 47 were confirmed and 28 fixed.

Program Repair

ATG has also been studied as a means to alleviate overfitting in automated program repair. Test-suite-based repair techniques generate patches that may overfit to the available tests and fail to generalize. An approach called UnsatGuided strengthens the repair constraint used by synthesis-based repair techniques by injecting additional automatically generated tests. In a study over the 224 bugs of the Defects4J repository, UnsatGuided was shown to be effective in alleviating one kind of overfitting issue—regression introduction—while having minimal positive impact on the other kind—incomplete fixing—due to the oracle problem.

Hardware Design Verification

In the hardware domain, ATG has long been central to simulation-based functional verification of processors and digital integrated circuits. Functional verification has been driven by the increasing complexity of designs (as documented in the International Technology Roadmap for Semiconductors, Design Chapter, 2005 edition), motivating tools such as Genesys-Pro, which introduced innovations in test program generation for functional processor verification. Foundational references include Bergeron's Writing Testbenches: Functional Verification of HDL Models and the IBM patent on coverage-directed test by Fine, Levinger, and Ziv.

A range of algorithmic techniques have been applied to ATG in this setting:

  • Evolutionary / genetic search. Corno et al. presented evolutionary test program induction for microprocessor design verification and a case study on automatic test program generation. Bose et al. proposed a genetic approach to automatic bias generation for biased random instruction generation. A genetic testing framework for digital integrated circuits was introduced by Yu, Fin, Fummi, and Rudnick.
  • Coverage-directed generation using Bayesian networks. Fine and Ziv described coverage directed test generation for functional verification using Bayesian networks, and Braun, Fine, and Ziv enhanced the efficiency of Bayesian-network-based coverage-directed test generation.
  • Activity monitors and stochastic approaches. A stochastic approach to test generation via activity monitors has also been investigated in the design automation literature.
  • Integer linear programming (ILP). ILP-based methods have been pursued as a route toward automating simulation-based design verification.

These approaches illustrate that ATG in hardware verification is closely coupled with coverage metrics, biased random instruction generation, and feedback from coverage analysis, rather than relying purely on unconstrained random stimulus.

Cross-Cutting Themes

Across domains, ATG research shares several recurring themes: (1) the use of feedback signals such as code coverage or structural program features to guide generation, (2) the need to address the oracle problem when no reliable specification exists, and (3) the integration of domain knowledge (e.g., structural and semantic characteristics of a target library, or coverage models of a hardware design) to make generated tests both valid and effective at triggering faults.

LINKED ENTITIES

2 links
A Genetic Testing Framework for Digital Integrated Circuits INTRODUCES
Automatic Test Program Generation: A Case Study INTRODUCES

CITATIONS

12 sources
12 citations
[1] Without effective ATG, developers risk introducing subtle data inconsistency bugs, compatibility issues, and security vulnerabilities that can affect large numbers of end users and cause severe financial losses. Multi-agent Assisted Automatic Test Generation for Java JSON Libraries
[2] JsonATG is a multi-agent ATG system for Java JSON libraries that uses historical bug information as seeds, a code summarization agent, a test validation agent, and agent-generated program mutation rules tailored to JJL characteristics, with post-processing for syntactic and semantic correctness. Multi-agent Assisted Automatic Test Generation for Java JSON Libraries
[3] Existing LLM-based methods like TitanFuzz and YanHui lack specialization in the JSON domain. Multi-agent Assisted Automatic Test Generation for Java JSON Libraries
[4] JsonATG achieved higher coverage than two state-of-the-art LLM-based test generation methods on a widely used JSON library, and with a $25 budget reported 59 bugs in fastjson, of which 47 were confirmed and 28 fixed. Multi-agent Assisted Automatic Test Generation for Java JSON Libraries
[5] UnsatGuild strengthens the repair constraint of synthesis-based repair by adding automatically generated tests, and on the 224 bugs of Defects4J was effective at alleviating regression introduction but had minimal positive impact on incomplete fixing due to the oracle problem. Alleviating Patch Overfitting with Automatic Test Generation: A Study of Feasibility and Effectiveness for the Nopol Repair System
[6] Genesys-Pro introduced innovations in test program generation for functional processor verification. Towards Automating Simulation-Based Design Verification Using ILP
[7] A genetic testing framework for digital integrated circuits was introduced by Yu, Fin, Fummi, and Rudnick at ICTAI. Towards Automating Simulation-Based Design Verification Using ILP
[8] Corno, Sanchez, Reorda, and Squillero published a case study on automatic test program generation and an evolutionary test program induction method for microprocessor design verification. Towards Automating Simulation-Based Design Verification Using ILP
[9] Bose, Shin, Rudnick, Dukes, and Abadir proposed a genetic approach to automatic bias generation for biased random instruction generation. Towards Automating Simulation-Based Design Verification Using ILP
[10] Fine and Ziv described coverage directed test generation for functional verification using Bayesian networks, and Braun, Fine, and Ziv enhanced the efficiency of Bayesian-network-based coverage-directed test generation. Towards Automating Simulation-Based Design Verification Using ILP
[11] A stochastic approach to test generation via activity monitors has been pursued in the design automation literature. Towards Automating Simulation-Based Design Verification Using ILP
[12] ILP-based methods have been pursued as a route toward automating simulation-based design verification. Towards Automating Simulation-Based Design Verification Using ILP