Skip to content
STIMSMITH

ARM ISA

Concept WIKI v1 · 8/12/2026

The ARM Instruction Set Architecture (ISA) is the silicon chip ISA developed and licensed by ARM Limited, and forms the target of the gem5 VLSI digital circuit simulator employed by ARM to test their systems. In the SearchSYS/SearchGEM5 research artifact, testing of the gem5 simulator focuses on the simulation of the ARM ISA, using differential testing between real ARM hardware and gem5 running in build/ARM configuration.

ARM ISA

Overview

The ARM Instruction Set Architecture (ISA) is the silicon chip ISA associated with ARM Limited. In the context of the SearchSYS/SearchGEM5 artifact (Even-Mendoza et al., ICSE-SEIP 2025), the ARM ISA is the specific architecture targeted by the gem5 VLSI digital circuit simulator that ARM employs to test their systems. The work explicitly focuses on the simulation of the ARM silicon chip ISA within gem5 and uses differential testing between the simulator and real ARM hardware to surface simulator bugs.

Role in the SearchSYS Artifact

The artifact at Zenodo record 14721385 describes reproducing the evaluation on ARM machines (arm64-ubuntu-2204 and Red Hat-based systems). To test the ARM ISA, gem5 must be built targeting the ARM architecture rather than X86, using SCons:

AFL_CC=/home/debian/AFLplusplus/afl-cc \
AFL_CXX=/home/debian/AFLplusplus/afl-c++ \
AFL_LINK=/home/debian/AFLplusplus/afl-c++ \
CXX=/home/debian/AFLplusplus/afl-c++ \
LINK=/home/debian/AFLplusplus/afl-c++ \
scons build/ARM/gem5.opt -j 4

During configuration, the build path build/ARM (not build/X86) must be selected, and the configuration log inspected to confirm that the ARM architecture has been correctly chosen. Executing gem5.opt -C then emits a license banner listing copyright holders including "Copyright (c) 2009-2011 ARM Limited", alongside other gem5 contributors.

Hardware Requirements for ARM ISA Testing

Reproducing the ARM ISA simulation experiments requires a physical ARM machine, since differential testing compares gem5's behavior against real ARM hardware:

  • Processor: ARM
  • Disk space: At least 80 GB free
  • RAM: 72 GB for full AFL++ fuzzing, or 16 GB for differential testing alone (without AFL++ instrumentation of gem5)
  • Operating systems tested: Ubuntu and Red Hat

Software Toolchain

The ARM ISA evaluation toolchain uses GCC-11, LLVM-13 (or newer), and Python 3.8/3.10. Additional required packages (installed via apt-get) include build-essential, python3-dev, automake, cmake, git, flex, bison, libglib2.0-dev, libpixman-1-dev, python3-setuptools, cargo, libgtk-3-dev, ninja-build, lld-13, llvm-13-dev, and clang-13. The build environment emits a benign -Wpointer-sign warning from afl-performance.c when using AArch64 system headers.

Related Concepts

  • gem5: The VLSI digital circuit simulator used by ARM to test their systems; built for the ARM ISA via the build/ARM/gem5.opt SCons target.
  • SearchSYS / SearchGEM5: The LLM + fuzzing + differential testing framework applied to the ARM ISA simulation in gem5.
  • AFL++: The fuzzer used to generate inputs exercising the ARM ISA simulation; instrumented builds of gem5 for ARM require the heavier 72 GB RAM configuration.
  • Differential testing: The technique of comparing ARM ISA execution between real ARM hardware and gem5 to identify mismatches as bugs.
  • ARM Limited: The ISA holder, listed as a gem5 copyright holder (2009-2011) in the simulator's license banner.

Caveats on Coverage

The provided evidence describes the ARM ISA only as it is exercised through the SearchSYS/SearchGEM5 artifact on gem5. No material in the provided chunks defines the ARM ISA's instruction formats, register set, execution modes, or revision history (e.g., ARMv7, ARMv8, ARM8v). Statements in the artifact about future adjustment to "ARM8v and fuzzed seeds" indicate the work targets an ARMv8-class ISA, but this is not explicitly defined in the evidence.

LINKED ENTITIES

1 links

CITATIONS

6 sources
6 citations
[1] The ARM ISA is the silicon chip Instruction Set Architecture whose simulation by gem5 is the focus of the SearchSYS testing work. Artifact of Search+LLM-based Testing for ARM Simulators - Zenodo
[2] gem5 is built for the ARM ISA via the SCons target build/ARM/gem5.opt, using AFL++ wrappers (afl-cc, afl-c++) when AFL++ instrumentation is desired. Artifact of Search+LLM-based Testing for ARM Simulators - Zenodo
[3] The gem5 ARM build's license banner lists ARM Limited as a copyright holder (2009-2011) alongside other gem5 contributors. Artifact of Search+LLM-based Testing for ARM Simulators - Zenodo
[4] Reproducing ARM ISA testing requires an ARM machine with 80 GB free disk and 72 GB RAM for AFL++ fuzzing, or 16 GB RAM for differential testing without AFL++ instrumentation of gem5. Artifact of Search+LLM-based Testing for ARM Simulators - Zenodo
[5] The supported operating systems for ARM ISA evaluation are Ubuntu (arm64-ubuntu-2204) and Red Hat-based systems, tested with GCC-11, LLVM-13, and Python 3.8/3.10. Artifact of Search+LLM-based Testing for ARM Simulators - Zenodo
[6] SearchSYS combines LLMs, fuzzing, and differential testing to find bugs in gem5's ARM ISA simulation; 4 unique bugs were reported and acknowledged by developers. Artifact of Search+LLM-based Testing for ARM Simulators - Zenodo