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Ariane

Concept WIKI v1 · 7/16/2026

Ariane is an open-source 64-bit application-class RISC-V processor core. The wiki article synthesizes its definition and role as an evaluation target in formal verification research from two primary arxiv papers and a recent review on scalable formal verification strategies for RISC-V control paths.

Overview

Ariane is an open-source, single-issue, in-order 64-bit RISC-V application-class processor core. It is designed to support a Linux-capable application environment and serves as a publicly available implementation target for research on RISC-V microarchitecture, security, and formal verification.

Description and Implementation

Ariane implements the 64-bit variant of the RISC-V ISA (RV64GC) in its baseline open-source configuration, with the tape-out measured instance corresponding to the RV64IMC subset. The core targets baseline "application class" functionality, including support for the Linux operating system and its application environment, virtual memory, caches, and multiple modes of privileged operation [arxiv:1904.05442v1].

Key measured characteristics of the taped-out Ariane instance fabricated in GlobalFoundries 22 FDX technology include:

  • Clock frequency: up to 1.7 GHz
  • Peak energy efficiency: up to 40 Gop/sW
  • ISA support: RV64GC baseline; measured silicon instance at RV64IMC [arxiv:1904.05442v1]

Role in Security Research

Ariane has been used as the experimental platform for evaluating microarchitectural covert-channel mitigations in combination with the seL4 microkernel's time-protection support. In that work, Ariane is described as "an open-source 64-bit application-class RISC-V core" used to evaluate five known covert channels and the efficacy of hardware time-protection mechanisms. The study reports that a single-instruction RISC-V ISA extension that flushes microarchitectural state enables the OS to close all five evaluated covert channels with low increases in context-switch costs and negligible hardware overhead [arxiv:2005.02193v1].

Role in Formal Verification Research

Ariane is one of three open-source RISC-V cores (alongside PicoRV32 and Rocket Core) used in a comparative study of formal verification methods for RISC-V control paths. The review reports the following verification runtime and bug-finding metrics for Ariane [1]:

  • Method: Parametric Invariants
  • Runtime: 4.8 hours
  • Bugs found: 5
  • Maximum memory: 5.5 GB

This places Ariane alongside Rocket Core and PicoRV32 as a representative open-source RISC-V target for empirical evaluation of proof-based, SMT-based, symbolic-execution-based, and AI-assisted verification techniques.

Related Research

The review [1] evaluates Ariane as a target for scalable formal verification strategies applied to RISC-V-based control paths, including:

  • Symbolic execution combined with bounded model checking (BMC), used to find assertion violations in RISC-V control FSMs with optimized solver backends such as Z3 and Yices.
  • Parameterized invariant-based proof frameworks that reuse property sets across different RISC-V configurations.
  • AI-enhanced proof-strategy prediction trees to streamline interactive theorem proving on industrial-scale RISC-V designs.

See Also

CITATIONS

6 sources
6 citations
[1] Ariane is an open-source, single-issue, in-order 64-bit RISC-V core (RV64GC) supporting a Linux application environment. The Cost of Application-Class Processing: Energy and Performance Analysis of a Linux-ready 1.7GHz 64bit RISC-V Core in 22nm FDSOI Technology
[2] A taped-out Ariane instance in GlobalFoundries 22 FDX runs at up to 1.7 GHz and achieves up to 40 Gop/sW peak efficiency, supporting virtual memory, caches, and multiple privileged modes. The Cost of Application-Class Processing: Energy and Performance Analysis of a Linux-ready 1.7GHz 64bit RISC-V Core in 22nm FDSOI Technology
[3] Ariane is described as an open-source 64-bit application-class RISC-V core used to evaluate five microarchitectural covert channels together with seL4 time protection. Prevention of Microarchitectural Covert Channels on an Open-Source 64-bit RISC-V Core
[4] A single-instruction RISC-V ISA extension flushing microarchitectural state was shown to close all five evaluated covert channels on Ariane with low context-switch cost increase and negligible hardware overhead. Prevention of Microarchitectural Covert Channels on an Open-Source 64-bit RISC-V Core
[5] In a comparative formal verification study, Ariane was verified using parametric invariants in 4.8 hours, finding 5 bugs and using up to 5.5 GB of memory. Scalable Formal Verification Strategies for RISC-V Based Control Paths: A Review
[6] The review evaluates Ariane alongside PicoRV32 and Rocket Core as open-source RISC-V targets for symbolic-execution-plus-BMC, parameterized invariant, and AI-assisted proof-strategy verification techniques. Scalable Formal Verification Strategies for RISC-V Based Control Paths: A Review