Architectural Validity Rules

Overview

Architectural validity rules are declarative constraints that describe legal or architecturally defined behavior of a hardware design under test. In model-based stimuli generation, they are part of the input knowledge used by a generic test-generation engine to create valid hardware tests for a given architecture.^[1]

These rules differ from user requests and expert-knowledge biases: user requests describe desired scenario features, expert knowledge describes preferred statistical distributions, while architectural validity rules define what must be true for the generated transaction stream to be architecturally meaningful.^[1]

Role in Model-Based Stimuli Generation

In the described model-based stimuli-generation approach, the generator is split into two major inputs and a generic engine:

a generic engine capable of generating tests for different hardware architectures;
an input model describing the target hardware architecture and expert knowledge;
test templates written by verification engineers to express partially specified verification scenarios.^[1]

Architectural validity rules reside in the model or knowledge base, alongside the declarative architectural description of the design under test. During generation, the engine must ensure that all user-defined and architectural validity rules are satisfied, while satisfying as many expert-knowledge rules as possible.^[1]

Examples

The evidence lists the following architectural validity rules:

Effective memory address calculation
```
Memory address = base-register data + offset
```
This rule defines how a memory address is computed for memory transactions.^[1]
Atomicity of aligned load-word instructions
```
If memory address is aligned to 4 bytes then Load-Word instruction is atomic
```
This rule specifies an architectural guarantee for aligned word loads.^[1]
Privileged instruction exception behavior
```
Privileged instruction when user-mode bit is on results in exception
```
This rule defines the expected architectural response when privileged instructions are attempted in user mode.^[1]

Relationship to Other Rule Types

The evidence distinguishes three categories of input constraints:

Rule category	Purpose	Example
User requests	Scenario-specific requirements from the verification plan	At least one operand in an `Add` instruction is larger than `9999`; the same processor issues 10 subsequent `Load` instructions to consecutive addresses.^[1]
Architectural validity rules	Mandatory architectural semantics and legality constraints	Address calculation, aligned load atomicity, privileged instruction exception behavior.^[1]
Expert knowledge	Statistical or heuristic guidance for generating useful tests	30% of `Add` instructions should result in `c = 0`; 20% of load/store instructions should cross page boundaries; 70% of transactions should contend on the same bus.^[1]

Architectural validity rules are therefore correctness constraints, whereas expert knowledge often expresses desired coverage distributions or stress conditions.

Use During Test Generation

A model-based stimuli generator uses architectural validity rules to determine whether candidate transactions are valid. The generator also uses a functional reference model to compute resource values after each generated transaction. These computed values are used both to generate subsequent transactions and to compare against design-simulator results; a mismatch indicates a design bug.^[1]

Generated tests may satisfy the same set of input rules while still reaching different scenarios, providing a form of uniform sampling over possible scenarios that satisfy the rules.^[1]

Importance

Architectural validity rules are central to scalable verification because they:

encode design semantics declaratively;
allow a generic generator to target different architectures by changing the model rather than the engine;
ensure generated tests remain legal or architecturally meaningful;
support automated satisfaction of complex rule sets together with user-defined constraints;
enable reusable architectural knowledge bases maintained by verification experts.^[1]