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Architectural Compliance Testing

Concept WIKI v1 · 7/6/2026

Architectural compliance testing refers to the process of verifying that processor implementations conform to a defined instruction set architecture (ISA) specification. In the context of RISC-V, architectural compliance testing is being formalized through a certification effort led by RISC-V International.

Architectural Compliance Testing

Overview

Architectural compliance testing is the practice of verifying that a processor or system-on-chip (SoC) implementation correctly conforms to the behavior, encoding, and semantics defined by its target instruction set architecture (ISA). It ensures that software written against the architecture specification will operate correctly on the hardware implementation, independent of vendor-specific extensions or microarchitectural choices.

RISC-V Compliance Context

Because RISC-V is an open ISA with broad adoption across embedded cores, processor clusters, and application processors, architectural compliance is particularly important. Implementations must demonstrate that they correctly execute the standard instruction set before custom extensions or vendor-specific features can be trusted in the broader ecosystem.

Key drivers for formal compliance testing in the RISC-V ecosystem include:

  • Diverse implementation space — A wide range of architectures and use cases means many independent implementations must each be verified against the same architectural spec.
  • Custom instruction verification — Vendor extensions must not break standard architectural behavior.
  • Compliance assurance — A repeatable, automatable check that a device matches the ISA contract.

Industry Coordination

According to public presentation material from Breker Verification Systems (Verification Futures Reading 2024), "RISC-V International [is] developing [a] certification committee to certify devices against architectural compliance tests." This indicates that the governing body for the RISC-V ISA is formalizing a certification program in which devices are evaluated against a defined suite of architectural compliance tests before being declared compliant.

Relationship to Broader Verification

Architectural compliance testing is one component of a larger RISC-V verification stack. While functional verification covers deep corner cases, microarchitectural behavior, and integration with SoC subsystems, architectural compliance testing focuses specifically on ISA-level conformance. The two activities are complementary: a design may pass compliance tests but still harbor microarchitectural bugs, and conversely may exhibit functional issues not directly tied to ISA semantics.

Practical Considerations

Effective architectural compliance testing typically requires:

  1. An authoritative, versioned architectural specification.
  2. A standardized, reusable test suite tied to the specification.
  3. An independent or neutral certification authority.
  4. Automation to scale across many implementations and revisions.

These are the same properties that RISC-V International's emerging certification committee is intended to provide for the RISC-V ecosystem.

LINKED ENTITIES

1 links
RISC-V International IMPLEMENTS

CITATIONS

2 sources
2 citations
[1] RISC-V International is developing a certification committee to certify devices against architectural compliance tests. RISC-V Core & SoC Verification: A New Normal in Verification Techniques (Verification Futures Reading 2024, Adnan Hamid, Breker Verification Systems)
[2] Compliance assurance is identified as a special RISC-V verification requirement, alongside custom instruction verification and supporting a broad range of architectures. RISC-V Core & SoC Verification: A New Normal in Verification Techniques (Verification Futures Reading 2024, Adnan Hamid, Breker Verification Systems)