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Application Scheduling

Concept WIKI v1 · 6/9/2026

Application scheduling is a design and compilation step in which the operations of an application are mapped onto the computational resources of a target architecture, taking into account resource availability, dependencies, and the cost of routing or binding. It is a recurring problem in both classical software schedulability analysis (e.g., under variable processor frequencies) and in specialized compilation flows for accelerators built around custom instructions, reconfigurable cells, or computing-in-memory (CIM) fabrics.

Application Scheduling

Definition

Application scheduling refers to the process of assigning the operations of an application — represented either as a graph of tasks or as a graph of computational patterns — to the available computational resources of a target architecture while respecting dependencies and constraints. In compilation-oriented contexts, it is typically performed jointly with related decisions such as instruction selection, binding (assignment of operations to specific functional units), and routing (placement/connection of operations on spatial resources).

Application Scheduling in the IFPEC Framework

In the IFPEC integrated design framework — a constraint programming (CP) based system for generating processor extensions and compiling applications onto them — application scheduling is one of the core design problems solved alongside extension identification, selection, binding, and routing [chunk:451e29a8-318b-49d4-b3ba-9769fc8370d3].

Key properties of the IFPEC approach to application scheduling include:

  • Graph-based representation. Both custom instructions (implemented as processor extensions) and the application itself are represented as graphs, which allows the CP framework to reason about them uniformly.
  • Constraint programming formulation. Subgraph isomorphism and connected component constraints are used to identify processor extensions and to perform their selection, application scheduling, binding, and routing within a single model.
  • Heterogeneous constraint combination. Different heterogeneous constraints can be combined, and the expressiveness of the CP framework makes it possible to solve extension selection, application scheduling, and binding simultaneously, improving the quality of generated results.
  • Target architecture. The scheduling problem assumes architectures composed of runtime reconfigurable cells (implementing the selected extensions) tightly connected to a host processor.
  • Subgraph isomorphism–driven identification. Because extensions are expressed as computational patterns, scheduling is coupled to the recognition of these patterns inside the application's graph, rather than being a purely temporal assignment problem.

Broader Contexts of Application Scheduling

Outside of IFPEC, application scheduling arises in several related settings documented in the public literature:

  • Variable-frequency software scheduling. Schedulability of software tasks can be experimentally estimated across a range of processor frequencies by injecting additional high-priority workload that emulates the effect of frequency scaling, with the resulting estimates used to inform dynamic voltage/frequency scaling (DVS/DFS) control algorithms.
  • Compilation for computing-in-memory (CIM) accelerators. Compilation methods targeting CIM accelerators focus on application scheduling optimization specific to CIM hardware. For example, the CMSwitch compiler integrates compute–memory mode switching into the CIM compilation optimization space, using dynamic programming and mixed-integer programming to identify optimal network segments and corresponding mode resource allocations for DNN applications.

Relationship to Other Concepts

  • IFPEC (Tool): IFPEC directly performs application scheduling as part of its constraint-programming design flow for processor extensions.
  • Custom instruction / processor extension selection: In IFPEC, application scheduling is solved jointly with the selection of which custom instructions to instantiate on the reconfigurable fabric.
  • Binding and routing: Application scheduling decisions are coupled to binding (mapping operations to units) and routing (placing/connecting them spatially on the reconfigurable cells).

See Also

LINKED ENTITIES

1 links
IFPEC USES

CITATIONS

5 sources
5 citations
[1] IFPEC is a constraint-programming design framework that performs application scheduling jointly with extension identification/selection, binding, and routing, using graph-based representations and subgraph isomorphism / connected component constraints. Constraint Programming Approach to Reconfigurable Processor Extension Generation and Application Compilation
[2] In IFPEC, the expressiveness of the CP framework allows extension selection, application scheduling, and binding to be solved simultaneously, improving the quality of generated results. Constraint Programming Approach to Reconfigurable Processor Extension Generation and Application Compilation
[3] The architectures targeted by IFPEC's application scheduling consist of runtime reconfigurable cells implementing selected processor extensions, tightly connected to a host processor. Constraint Programming Approach to Reconfigurable Processor Extension Generation and Application Compilation
[4] Software schedulability at varied processor frequencies can be estimated experimentally by injecting additional high-priority workload to emulate frequency reduction, and such estimates inform DVS/DFS control algorithms. Experimental Software Schedulability Estimation For Varied Processor Frequencies
[5] Application scheduling is a key compilation optimization target for computing-in-memory (CIM) accelerators, and the CMSwitch compiler integrates compute–memory mode switching into the scheduling optimization space to better serve DNN applications. Be CIM or Be Memory: A Dual-mode-aware DNN Compiler for CIM Accelerators