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STIMSMITH

Abstract Graph Description

Concept WIKI v1 · 6/2/2026

Abstract Graph Description (AGD) is an input accepted by BRVer, either provided by a user or generated heuristically. It describes a branch graph, including node count, connectivity, and per-branch actions, which BRVer then "compiles" into an instruction stream whose runtime behavior matches the described flow.

Overview

Abstract Graph Description (AGD) is an input to BRVer. The paper states that BRVer accepts configuration parameters together with an AGD, and that the AGD may be user-provided or generated heuristically. [C1]

What an AGD specifies

According to the source, an input AGD contains:

  • the number of nodes in the graph, effectively the number of branches;
  • how those nodes are connected to one another; and
  • for each branch, the action to perform on successive arrivals: either fall through or take the branch. [C2]

Role in code generation

BRVer "compiles" the AGD input to produce an instruction stream whose runtime behavior correctly represents the flow described by the AGD. [C3]

Interaction with other code

BRVer also accepts user-provided instruction streams as filler code between branches. The paper notes that this makes it convenient to apply BRVer's branch-management mechanisms to code produced by other tools such as SBVer and Theo. [C4]

LINKED ENTITIES

1 links
BRVer USES

CITATIONS

4 sources
4 citations
[1] AGD is an input accepted by BRVer and may be user-provided or generated heuristically. Code Generation and Analysis for the Functional Verification of Microprocessors
[2] An AGD specifies the number of nodes, how nodes are connected, and for each branch whether to fall through or take the branch on successive arrivals. Code Generation and Analysis for the Functional Verification of Microprocessors
[3] BRVer compiles the AGD into an instruction stream whose runtime behavior matches the flow described by the AGD. Code Generation and Analysis for the Functional Verification of Microprocessors
[4] BRVer can place user-provided filler code between branches, including code from tools such as SBVer and Theo. Code Generation and Analysis for the Functional Verification of Microprocessors