riscv_instr_sequence.sv

Overview

riscv_instr_sequence.sv is a SystemVerilog source file in the chipsalliance/riscv-dv repository, located under the src/ directory on the repository’s master branch.^[1] The surrounding repository is described as a “Random instruction generator for RISC-V processor verification,” indicating that this file belongs to the RISC-V DV verification stimulus-generation codebase.^[1]