2026-05-27
5 items 190 entities 245 connections
Processed 65 entities and 89 relations.
TestRIG Direct Instruction Injection Tandem Execution Randomized Instruction Generation RVFI-DII RVFI QCVEngine RISCV-DV PyH2P Spike QEMU QuickCheck JasperGold C-Reduce sailcov Genesys-Pro Verification Engine (VEngine) Tandem Verification Model-based Random Testing Test Case Shrinking Directed-Random Test Sequence Generation Symbolic QED Counterexample-Driven Development Architectural Coverage RISC-V Formal Interface Instruction Sequence Generation Execution Trace Comparison Register Reuse Memory Concurrency Testing Regression Testing Constraint Solving for Instruction Generation CHERI Security Extension RISC-V Sail Language Sail RISC-V Model RVBS Ibex Piccolo Flute Toooba RTL Formal Verification Randomized Testing of RISC-V CPUs using Direct Instruction Injection Alexandre Joannou Peter Rugg Jonathan Woodruff Franz A. Fuchs Marno van der Maas Matthew Naylor Michael Roe Robert N. M. Watson Peter G. Neumann Simon W. Moore Claire Wolf Brian Campbell DARPA University of Cambridge Axe Memory Consistency Checker Sequence Import/Export Non-shrinkable Sequences Assertions in Instruction Sequences Pipeline Performance Testing L3 Specification Language riscv-tests Tandem Execution
MorFuzz: Fuzzing Processor via Runtime Instruction Morphing enhanced Synchronizable Co-simulation
source →Processed 46 entities and 65 relations.
MorFuzz Runtime Instruction Morphing Synchronizable Co-simulation Stimulus Template Coverage-Guided Fuzzing Processor Fuzzing Hardware Fuzzing RTL Simulation ISA Simulation RISC-V Instruction Set Architecture Instruction Stream Generation Processor State Coverage Co-simulation State Verification Instruction Field Level Mutation Program Semantic Level Mutation Instruction Shuffle Control Register Coverage State Synchronization Constrained Random Verification Formal Verification DifuzzRTL TheHuzz riscv-dv Spike Synopsys VCS FIRRTL riscv-torture CVA6 Rocket BOOM Morpher Hardware Logic Block Fuzzing Execution Environment Random Number Generator Testing Block Pipeline Hazard Generation Watchpoint Instruction MorFuzz: Fuzzing Processor via Runtime Instruction Morphing enhanced Synchronizable Co-simulation Jinyan Xu Yiyuan Liu Sirui He Haoran Lin Yajin Zhou Cong Wang Zhejiang University City University of Hong Kong UC Berkeley
Processed 18 entities and 21 relations.
Instiller RTL Fuzzing Ant Colony Optimization Variant of Ant Colony Optimization Input Instruction Distillation Hardware-Based Seed Selection Hardware-Based Mutation Interruption and Exception Simulation DiFuzzRTL RTL CPU Bug Detection Instruction Sequence Seed Selection Meltdown Spectre Pentium FDIV Bug Broadwell MCE Bug Ryzen Segfault Bug
Processed 33 entities and 29 relations.
RISC-V ISA CPU microarchitecture processor verification pipeline speculative execution out-of-order execution Spectre Meltdown constrained-random instruction generation simulation-based verification formal verification hardware-assisted validation virtual prototyping simulation acceleration hardware prototyping reference model comparison coverage-driven verification custom instruction verification UVM SystemVerilog SystemVerilog assertions RTL ALU SoC integration instruction sequence generation RISC-V International ARM x86 test generator security verification custom instruction verification
Processed 28 entities and 41 relations.
RISCV-DV Spike constrained-random test generation co-simulation UVM UVM scoreboard UVM agent virtual sequence SystemVerilog Assertions functional coverage RISC-V Vector extension (RVV) Open Vector Interface (OVI) reference model random RISC-V assembly test generation CI/CD pipeline Jenkins GitLab Vector Processing Unit (VPU) RTL blacklisting instructions unordered floating-point reduction reference model UVM testbench Functional Verification of a RISC-V Vector Accelerator Barcelona Supercomputing Center SemiDynamics European Processor Initiative Google RISC-V ISA