Rashinkar, P., Paterson, P., Singh, L.: System-on-a-chip Verification – Methodology and Techniques. Kluwer Academic Publishers, Dordrecht (2001)

MATH Google Scholar

Albin, K.: Nuts and Bolts of Core and SoC Verification. In: 38th Design Automation Conference, DAC 2001 (2001)

Google Scholar

Berry, G., Bouali, A., Dormoy, J., Blanc, L.: Top-level Validation of System-on-Chip in Esterel Studio. In: Proceedings of the IEEE International High Level Design Validation and Test Workshop (2001)

Google Scholar

Brahme, et al. The Transaction-Based Verification Methodology, Cadence Berkeley Labs, Technical Report # CDNL-TR-2000-0825 (August 2000)

Google Scholar

Aharon, A., Goodman, D., Levinger, M., Lichtenstein, Y., Malka, Y., Metzger, C., Molcho, M., Shurek, G.: Test Program Generation for Functional Verification of PowerPC Processors in IBM. In: Proceedings of the Design Automation Conference (1995)

Google Scholar

Bin, E., Emek, R., Shurek, G., Ziv, A.: Using a constraint satisfaction formulation and solution techniques for random test program generation. IBM Systems Journal 41(3) (2002)

Google Scholar

Allon, A., Almog, E., Fournier, L., Marcus, E., Rimon, M., Vinov, M., Ziv, A.: Genesys Pro: Innovations in Test Program Generation for Functional Processor Verification. IEEE Design & Test of Computers (2004)

Google Scholar

Emek, R., Jaeger, I., Naveh, Y., Bergman, G., Aloni, G., Katz, Y., Farkash, M., Dozoretz, I., Goldin, A.: X-Gen: A Random Test-Case Generator for Systems and SoCs. In: Proceedings of the IEEE International High Level Design Validation and Test Workshop (2002)

Google Scholar

Practical Approaches to SOC Verification, Mosensoson G, http://www.verisity.com/download/practical_soc_verification.pdf

Besyakov, V., Shleifman, D.: Constrained Random Test Environment for SoC Verification using VERA, SNUG Boston (2002)

Google Scholar

http://www-03.ibm.com/systems/power/

Pham, D., Asano, S., Bolliger, M., Day, M.N., Hofstee, H.P., Johns, C., Kahle, J., Kameyama, A., Keaty, J., Masubuchi, Y., Riley, M., Shippy, D., Stasiak, D., Suzhoki, M., Wang, M., Warnock, J., Weitzel, S., Wendel, D., Yamazaki, T., Yazawa, K.: The Design and Implementation of a First- Generation CELL Processor. In: Proceedings of the IEEE International Solid-State Circuits Conference, ISSCC 2005 (2005)

Google Scholar