SPARCv8
ToolFirst seen 7/7/2026
Last seen 7/7/2026
Evidence 4 chunks
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5 connectionsThe experimental evaluation of μGP was performed on a SPARCv8 microprocessor.
The SPARCv8 pipeline testability is the target problem addressed by the approach.
The SPARCv8 is available as a synthesizable VHDL model.
The SPARCv8 VHDL model produces a netlist after synthesis numbering about 65,000 gates.
The FPGA-based hardware emulator is used to evaluate the SPARCv8 design.