PEAKTOP Toolchain
The PEAKTOP Toolchain is the software toolchain associated with the PEAKTOP processor architecture, developed as a deliverable of the MORAL project (Horizon 2020 Space Theme Programme, Grant Agreement No. 870365), which ran from January 2020 to April 2023. It is explicitly listed as a component of the MORAL Software work-stream alongside the Compiler and RTOSK (Real-Time Operating System Kernel) [1].
Context within MORAL
The MORAL project is coordinated by IHP (Innovations for High Performance Microelectronics) and brings together five partners with the objective of developing a completely European, ITAR-free microcontroller for space applications. The microcontroller is based on the novel PEAKTOP architecture, which features a freely available, open Instruction Set Architecture (ISA). The toolchain forms a core part of MORAL's deliverable set, supporting:
- A formally-verified C compiler
- A Real-Time Operating System (RTOS)
- A complete toolchain for software development on the PEAKTOP core
The toolchain is designed to support the PEAKTOP core's mixed-criticality features, which allow multiple functions with differing criticality and assurance levels to co-exist on the microcontroller, including dynamically grouped General Purpose Register (GPR) banks and Dual-, Triple-, or Quadruple-Modular Redundant (DMR/TMR/QMR) fault-tolerance modules.
Development Status
The toolchain was developed and matured as part of the MORAL Software agenda item, reported at the 9th International Workshop on Analogue and Mixed-Signal Integrated Circuits for Space Applications (AMICSA '22) on 3 June 2022. Its development aligns with broader project goals of irradiation testing, demonstrator board creation, and aggressive exploitation for market entry.
Partners Contributing to the Toolchain
According to the AMICSA '22 presentation [1], MORAL project partners contributing to the RTOS, compiler, and toolchain effort include Absint (compiler analysis expertise) and SYSGO (RTOS development, branded as "Embedding Innovations"), together with the lead architect IHP and other consortium partners.
Key Characteristics
- Open ISA Compatibility: Built around PEAKTOP's open Instruction Set Architecture, enabling full control over compiler optimizations and code generation for the microcontroller.
- Formal Verification: The C compiler component is formally verified, providing high assurance suitable for safety-critical space applications.
- Mixed-Criticality Support: Designed to leverage the PEAKTOP architecture's mixed-criticality features and modular redundancy capabilities.
- Space-Grade Software Stack: Integrates with the RTOS to deliver a complete execution platform for rad-hard European space microcontrollers.