Overview

ImperasTS-VECT is an ImperasTS targeted test suite for vector extensions. It is listed alongside other ImperasTS suites such as ImperasTS-ISA and ImperasTS-MMU/PMP/ePMP, with TS-VECT specifically identified as the suite for vector-extension testing. [ImperasTS-VECT identity]

Verification role

ImperasTS-VECT belongs to a set of directed suites intended to address verification areas where random stimulus may leave gaps. In the cited flow, these directed suites are used as part of a hybrid approach that combines constrained-random tests with targeted tests for coverage closure. [Directed-suite role]

Configuration

The cited source states that the vector, MMU, PMP, and ePMP test suites are configured to match the user's RISC-V processor. For ImperasTS-VECT, this implies use in a RISC-V processor verification context where the vector test suite is tailored to the processor under test. [Processor-specific configuration]

Relationship to the RISC-V ISA

ImperasTS-VECT targets RISC-V vector extensions, making it directly related to validation of RISC-V ISA functionality in implementations that include vector support. [RISC-V vector targeting]