Skip to content
STIMSMITH

Imperas RISC-V Processor Verification IP (VIP)

Tool WIKI v1 · 9/24/2026

Imperas RISC-V Processor Verification IP (VIP) is a commercial verification solution from Imperas Software Ltd that provides architectural validation test suites and a golden reference model for verifying RISC-V processor RTL implementations against the ratified and near-ratified RISC-V ISA specifications. The VIP employs a step-and-compare methodology within a SystemVerilog UVM environment and ships with open-source test suites totaling over 3.5 million instructions.

Overview

Imperas RISC-V Processor Verification IP (VIP) is a commercial verification solution provided by Imperas Software Ltd that targets RISC-V processor implementation verification. The VIP combines a golden reference model of the RISC-V ISA with architectural validation test suites, directed-test generation capabilities, and built-in functional coverage monitors. Together these components enable design teams to verify RTL processor implementations against the ratified and near-ratified RISC-V specifications using a step-and-compare methodology.

Verification Methodology

The VIP is intended to be used to verify an RTL processor implementation against the Imperas golden reference model, encapsulated within a SystemVerilog UVM environment. The step-and-compare approach supports asynchronous events and is designed to provide a seamless transition to debug analysis when an issue is found. Imperas motivates early verification on the basis that late-stage design bugs can have significant economic consequences, citing as a historical example the 1994 Intel Floating Point bug, which was reported at the time as a pre-tax charge of $475 million.

Floating-Point Validation Test Suites

In February 2021, Imperas announced an extension to the RISC-V VIP covering the RISC-V floating-point specifications:

  • RV32F — 32-bit Single-Precision Floating-Point (IEEE 754-2008)
  • RV64F — 64-bit Single-Precision Floating-Point (IEEE 754-2008)
  • RV64D — 64-bit Double-Precision Floating-Point (IEEE 754-2008)

The test suites target the ratified RISC-V floating-point standard extensions and are described as complementing the industry adoption of the Imperas RISC-V verification reference model.

Open-Source Architectural Validation Test Suites

The VIP is distributed alongside freely available open-source test suites that together total over 3.5 million instructions and are intended for ISA architectural compliance validation. As of the announcement they include:

  • Test suites for the ratified RV32F, RV64F, and RV64D floating-point specifications
  • Test suites for the ratified RV32/64IMC specifications
  • A test suite for RISC-V Vectors (configured for spec 0.8, xlen:32, elen:32, vlen:256, slen:256, FP:IEEE754; with other configurations of xlen, elen, vlen, slen and spec versions 0.9 and 1.0 draft available on request to Imperas)
  • A test suite for RV32/64K Crypto (scalar) at the 0.8.0 draft specification
  • A test suite for RV32/64B Bit Manipulation at the 0.93 draft specification

Imperas explicitly notes that these architectural validation test suites are not comprehensive hardware design verification suites that prove hardware is bug-free.

Coverage

The Imperas RISC-V golden reference model is enhanced with built-in monitors that provide instruction and architectural functional coverage metrics during simulation, without requiring post-simulation processing or log-file analysis.

Free Reference Model and Simulator

The VIP ecosystem is paired with riscvOVPsimPlus, a free RISC-V reference model and simulator that has been widely adopted across the RISC-V verification ecosystem. riscvOVPsimPlus supports the ratified RV32/64 IMAFDC specifications as well as near-ratified ISA extensions including:

  • Vector ("V")
  • Hypervisor ("H")
  • Bit Manipulation ("B")
  • Crypto (Scalar)

More details on test benches using the Imperas RISC-V verification reference models are available at the Imperas RISC-V page (https://www.imperas.com/riscv).

LINKED ENTITIES

1 links
Imperas Floating-Point Architectural Validation Test Suites PART_OF

CITATIONS

7 sources
7 citations
[1] Imperas RISC-V VIP is a commercial verification solution from Imperas Software Ltd that combines a golden reference model with architectural validation test suites for RISC-V processor verification. Imperas Leads The RISC-V Processor Verification Ecosystem - Embedded Computing Design
[2] The VIP supports verification of RTL implementations against the golden reference model using a step-and-compare methodology inside a SystemVerilog UVM environment, supporting asynchronous events. Imperas Leads The RISC-V Processor Verification Ecosystem - Embedded Computing Design
[3] In February 2021, Imperas announced floating-point architectural validation test suites covering RV32F, RV64F, and RV64D based on the IEEE 754-2008 standard. Imperas Leads The RISC-V Processor Verification Ecosystem - Embedded Computing Design
[4] The Imperas architectural validation test suites are open source, total over 3.5 million instructions, and cover RV32F, RV64F, RV64D, RV32/64IMC, RISC-V Vectors, RV32/64K Crypto (scalar 0.8.0 draft), and RV32/64B Bit Manipulation (0.93 draft). Imperas Leads The RISC-V Processor Verification Ecosystem - Embedded Computing Design
[5] The Imperas architectural validation test suites are for ISA architectural compliance validation and are not comprehensive hardware design verification suites that prove hardware is bug-free. Imperas Leads The RISC-V Processor Verification Ecosystem - Embedded Computing Design
[6] The Imperas RISC-V golden reference model includes built-in monitors that provide instruction and architectural functional coverage metrics without post-simulation processing. Imperas Leads The RISC-V Processor Verification Ecosystem - Embedded Computing Design
[7] The free riscvOVPsimPlus reference model and simulator supports ratified RV32/64 IMAFDC specifications as well as near-ratified Vector, Hypervisor, Bit Manipulation, and Crypto (Scalar) extensions. Imperas Leads The RISC-V Processor Verification Ecosystem - Embedded Computing Design