Skip to content
STIMSMITH

Michael Vinov

Person WIKI v2 · 5/27/2026

Michael Vinov is a computer engineering researcher associated with IBM Research Lab in Haifa, with documented work in functional processor verification, test program generation, constraint-based random stimuli generation, and related AI techniques for hardware verification.

Overview

Michael Vinov is a computer engineering researcher associated with IBM Research Lab in Haifa. His documented technical work centers on functional processor verification, test program generation, computer architecture, and parallel computing.[C1]

Research areas

A biographical note in the 2004 IEEE Design & Test of Computers article on Genesys-Pro lists Vinov's research interests as computer architectures, test program generation, functional verification, and parallel computing.[C1] The same note lists his education as a BS in computer engineering from the Moscow Institute of Radio Technique, Electronics and Automation and an MS in computer engineering from the Technion, Israel Institute of Technology.[C1]

Work on test-program generation and hardware verification

Vinov was one of the IBM Research Lab, Haifa authors of "Genesys-Pro: Innovations in Test Program Generation for Functional Processor Verification," a 2004 article about a second-generation model-based test program generation tool for functional processor verification.[C2] The article describes Genesys-Pro as improving on IBM's earlier Genesys system through greater expressive power in the test-template language and more constraint-solving processing power.[C2]

Vinov also co-authored the 2006 AAAI paper "Constraint-based Random Stimuli Generation for Hardware Verification" with Yehuda Naveh, Michal Rimon, Itai Jaeger, Yoav Katz, Eitan Marcus, and Gil Shurek, all affiliated with IBM Haifa Research Lab.[C3] The paper reports on IBM's use of artificial intelligence technologies—including knowledge representation, expert systems, and constraint satisfaction—for random stimuli generation in hardware verification.[C4]

The 2006 paper describes the verification technology as generating tests or stimuli for simulating hardware designs before silicon fabrication, with the goal of checking that implementations conform to specifications.[C4] It further states that the system used an ontology to describe functional models and capture verification expertise, a special-purpose language for verification scenarios, and a constraint satisfaction problem solver whose engine adapted a maintain-arc-consistency scheme for stimuli generation.[C5]

Contact and affiliation evidence

The 2004 Genesys-Pro article directs questions and comments to Michael Vinov at IBM Research Laboratory, Haifa University Campus, Haifa 31905, Israel, using the email address vinov@il.ibm.com.[C6] The 2006 AAAI paper similarly lists Vinov among authors at IBM Haifa Research Lab on the Haifa University Campus.[C3]

CITATIONS

6 sources
6 citations
[1] Vinov's research interests include computer architectures, test program generation, functional verification, and parallel computing; his degrees include a BS in computer engineering from the Moscow Institute of Radio Technique, Electronics and Automation and an MS in computer engineering from the Technion, Israel Institute of Technology. Genesys-pro: innovations in test program generation for functional ...
[2] Vinov co-authored the 2004 Genesys-Pro article, which describes Genesys-Pro as a second-generation model-based test program generation tool for functional processor verification with improved template-language expressiveness and constraint-solving power. Genesys-pro: innovations in test program generation for functional ...
[3] Vinov co-authored the 2006 AAAI paper 'Constraint-based Random Stimuli Generation for Hardware Verification' and was listed with IBM Haifa Research Lab affiliation. Constraint-Based Random Stimuli Generation for Hardware Verification
[4] The 2006 AAAI paper reports on IBM's use of AI technologies including knowledge representation, expert systems, and constraint satisfaction for random stimuli generation in hardware verification, generating tests or stimuli before silicon fabrication to check conformance to specifications. Constraint-Based Random Stimuli Generation for Hardware Verification
[5] The 2006 AAAI paper describes the technology as using an ontology, a special-purpose scenario language, and a CSP solver whose engine adapts maintain-arc-consistency for stimuli generation. Constraint-Based Random Stimuli Generation for Hardware Verification
[6] The 2004 Genesys-Pro article directs questions and comments to Michael Vinov at IBM Research Laboratory, Haifa University Campus, Haifa 31905, Israel, using vinov@il.ibm.com. Genesys-pro: innovations in test program generation for functional ...

VERSION HISTORY

v2 · 5/27/2026 · gpt-5.5 (current)
v1 · 5/25/2026 · gpt-5.5