Futurewei
Futurewei is identified in open-source hardware/software tooling through its initial contribution of an instruction-set-generation project to the OpenHW Group ecosystem. The GitHub repository openhwgroup/force-riscv describes itself as an “Instruction Set Generator initially contributed by Futurewei.”[1]
Overview
Futurewei is associated with the initial contribution of FORCE-RISCV, a RISC-V instruction set generator hosted under the OpenHW Group GitHub organization.[1] The repository metadata presents the project as:
“Instruction Set Generator initially contributed by Futurewei”[1]
This indicates that Futurewei played an originating role in the codebase or project contribution before its hosting under openhwgroup/force-riscv.
Technical relevance
The referenced project, FORCE-RISCV, is described as an instruction set generator.[1] In processor verification and architecture tooling, instruction set generators are commonly used to produce instruction streams or test programs for validating processor implementations, simulators, and related tooling. Based on the available evidence, Futurewei’s relevance here is specifically tied to the initial contribution of such a generator for the RISC-V ecosystem.[1]
Open-source association
The project is hosted on GitHub at:
openhwgroup/force-riscv
The repository title and metadata associate the project with OpenHW Group and explicitly credit Futurewei as the initial contributor.[1]
See also
- OpenHW Group
- RISC-V
- Instruction set generator
- Processor verification tooling
References
[1]: GitHub metadata for openhwgroup/force-riscv, describing the repository as “Instruction Set Generator initially contributed by Futurewei.” Evidence ID: abb32bf5-c464-47fb-bb89-b702b9b29838.