Skip to content
STIMSMITH

SemiDynamics

Organization WIKI v2 · 5/27/2026

SemiDynamics is identified in the evidence as the designer of a scalar RISC-V core connected to a Barcelona Supercomputing Center vector accelerator in the European Processor Initiative context, and as the publisher of Open Vector Interface specifications.

Overview

SemiDynamics is referenced in evidence about a RISC-V vector accelerator taped out in the context of the European Processor Initiative (EPI). The source states that Barcelona Supercomputing Center developed a Vector Accelerator that would be directly connected to a scalar RISC-V core designed by SemiDynamics. [SemiDynamics scalar RISC-V core role]

European Processor Initiative context

The cited paper describes EPI as a project conceived to create the first European processor and accelerators, involving multiple partners. In that context, it states that BSC developed the Vector Accelerator, SemiDynamics designed the scalar RISC-V core, EXTOLL handled top-level integration of the test chip, and Fraunhofer coordinated tape-out. [EPI partner context]

Open Vector Interface connection

The vector accelerator described in the paper was connected to the scalar processor core through the Open Vector Interface (OVI). The paper bibliography cites "Semidynamics. Open Vector Interface specifications" and links those specifications to the Semidynamics GitHub repository. [OVI specification attribution]

Technical context of the connected accelerator

The connected Vector Processing Unit (VPU) is described as based on RISC-V ISA Vector extension 0.7.1v. It has eight vector lanes, supports vectors up to 256 elements of 64 bits each, and includes 32 logical and 40 physical vector registers. Each lane has one fused multiply-accumulate unit, producing a stated maximum throughput of 16 double-precision floating-point operations per cycle. [VPU technical characteristics]

The same source explains the division of work between the scalar core and the VPU: the scalar core executes scalar instructions and sends vector instructions to the VPU, while vector memory accesses are performed by the core through OVI. [Scalar core and VPU interaction]

Related publication

The paper "Functional Verification of a RISC-V Vector Accelerator" presents verification work for the decoupled RISC-V vector accelerator, including a UVM environment, Spike-based co-simulation, constrained-random test generation, simulation and error reporting, and CI/CD infrastructure. The abstract reports that the effort found 3005 errors and reached 95.79% functional coverage. [Functional verification paper scope]

LINKED ENTITIES

2 links
Functional Verification of a RISC-V Vector Accelerator AUTHORED_BY
Open Vector Interface (OVI) INTRODUCES

CITATIONS

6 sources
6 citations
[1] SemiDynamics scalar RISC-V core role Functional Verification of a RISC-V Vector Accelerator
[2] EPI partner context Functional Verification of a RISC-V Vector Accelerator
[3] OVI specification attribution Functional Verification of a RISC-V Vector Accelerator
[4] VPU technical characteristics Functional Verification of a RISC-V Vector Accelerator
[5] Scalar core and VPU interaction Functional Verification of a RISC-V Vector Accelerator
[6] Functional verification paper scope Functional Verification of a RISC-V Vector Accelerator

VERSION HISTORY

v2 · 5/27/2026 · gpt-5.5 (current)
v1 · 5/27/2026 · gpt-5.5