lowRISC

Organization WIKI v1 · 5/28/2026

lowRISC is a not-for-profit engineering company that creates and maintains commercial-grade open-source silicon designs through a collaborative Silicon Commons approach. It maintains Ibex, a production-quality open-source 32-bit RISC-V CPU core used in contexts such as OpenTitan.

lowRISC

lowRISC is a not-for-profit engineering company that creates and maintains commercial-grade open-source silicon designs through its collaborative Silicon Commons approach.

Maintained silicon designs

The organization maintains Ibex, described as a production-quality open-source 32-bit RISC-V CPU core written in SystemVerilog. Ibex is heavily parameterizable, suited for embedded control applications, has undergone extensive verification, and has seen multiple tape-outs.

Ibex supports the RISC-V Integer (I) or Embedded (E), Integer Multiplication and Division (M), Compressed (C), and B/Bit Manipulation extensions.

Ibex in OpenTitan

Ibex is used in OpenTitan, an open-source silicon Root of Trust project. The cited source describes OpenTitan as a secure chip intended to serve as a foundational security component, providing trustworthy functions that other parts of a device or system can use to establish strong security.

Verification approach used for Ibex

Ibex is verified using a UVM-based testbench with co-simulation against the Spike instruction-set-simulator reference model. The testbench runs binaries generated from source produced by the RISC-DV random instruction generator.

The Ibex testbench also provides randomized memory timings, memory errors, interrupts, and debug requests, and it includes a comprehensive test plan and coverage plan. Because Ibex has many parameters and a large configuration space, verification closure targets a set of supported configurations rather than every possible parameter set.

The cited source states that current verification-closure effort is focused on the OpenTitan configuration, which is the only configuration with nightly regression runs. It also reports that verification maturity is tracked using Verification Stages defined by the OpenTitan project, with 90% code and functional coverage achieved, more than 90% regression pass rate, and the test plan and coverage plan fully implemented but not yet closed. Nightly regression results for the OpenTitan Ibex configuration are published at https://ibex.reports.lowrisc.org/opentitan/latest/report.html.

CITATIONS

9 sources

9 citations

[1] lowRISC is a not-for-profit engineering company that creates and maintains commercial-grade open-source silicon designs through a collaborative Silicon Commons approach. [PDF] UVM based design veri cation of a RISC-V CPU core - POLITesi

[2] lowRISC maintains Ibex, a production-quality open-source 32-bit RISC-V CPU core written in SystemVerilog. [PDF] UVM based design veri cation of a RISC-V CPU core - POLITesi

[3] Ibex is heavily parameterizable, suited for embedded control applications, has undergone extensive verification, and has seen multiple tape-outs. [PDF] UVM based design veri cation of a RISC-V CPU core - POLITesi

[4] Ibex supports the RISC-V I or E, M, C, and B/Bit Manipulation extensions. [PDF] UVM based design veri cation of a RISC-V CPU core - POLITesi

[5] Ibex is used in OpenTitan, an open-source silicon Root of Trust project described as a secure chip providing trustworthy functions for strong device or system security. [PDF] UVM based design veri cation of a RISC-V CPU core - POLITesi

[6] Ibex is verified using a UVM-based testbench with co-simulation against the Spike ISS reference model and binaries generated from RISC-DV random-instruction-generator output. [PDF] UVM based design veri cation of a RISC-V CPU core - POLITesi

[7] The Ibex testbench provides randomized memory timings, memory errors, interrupts, and debug requests, and implements a comprehensive test plan and coverage plan. [PDF] UVM based design veri cation of a RISC-V CPU core - POLITesi

[8] Ibex verification closure targets supported configurations, with current effort focused on the OpenTitan configuration, which has nightly regression runs. [PDF] UVM based design veri cation of a RISC-V CPU core - POLITesi

[9] The cited source reports 90% code and functional coverage, more than 90% regression pass rate, and fully implemented but not yet closed test and coverage plans for Ibex verification maturity tracking. [PDF] UVM based design veri cation of a RISC-V CPU core - POLITesi