chipsalliance

Overview

chipsalliance is evidenced in the supplied GitHub metadata as the owner login and namespace for the public repository chipsalliance/riscv-dv. The metadata identifies repository ID 167140400, repository name-with-owner chipsalliance/riscv-dv, and Git import URL https://github.com/chipsalliance/riscv-dv.git.[C1]

The supplied project README describes RISCV-DV as a SystemVerilog/UVM-based open-source instruction generator for RISC-V processor verification.[C2] A Design & Reuse article states that CHIPS Alliance developed an open-source riscv-dv random instruction generator for RISC-V processor verification.[C3]

riscv-dv repository

The primary repository evidenced for this entity is:

chipsalliance/riscv-dv

GitHub page metadata for src/riscv_instr_sequence.sv identifies the repository as chipsalliance/riscv-dv, marks it public, and gives the repository description as:

Random instruction generator for RISC-V processor verification[C1]

The same GitHub metadata shows the referenced source-file page title as riscv-dv/src/riscv_instr_sequence.sv at master · chipsalliance/riscv-dv and the Open Graph URL as https://github.com/chipsalliance/riscv-dv/blob/master/src/riscv_instr_sequence.sv.[C1]

Supported verification features

The riscv-dv README lists support for the following verification features:[C2]

• RISC-V instruction sets RV32IMAFDC and RV64IMAFDC.
• Privileged modes: machine mode, supervisor mode, and user mode.
• Page-table randomization and exception support.
• Privileged CSR setup randomization and a privileged CSR test suite.
• Trap and interrupt handling.
• MMU stress-test suites.
• Sub-program generation and random program calls.
• Illegal-instruction and HINT-instruction generation.
• Random forward and backward branch instructions.
• Mixing directed instructions with random instruction streams.
• Debug-mode support with a fully randomized debug ROM.
• Instruction-generation coverage modeling.
• Handshake communication with a testbench.
• Support for hand-coded assembly tests.
• Co-simulation with multiple instruction-set simulators: Spike, riscv-ovpsim, Whisper, and sail-riscv.

Generator structure

The Design & Reuse article describes the open-source riscv-dv project as defining a SystemVerilog UVM-based class structure used in RISC-V IP verification. It states that generated random tests can be added directly to run with design IP, and that assembly-program sections such as initialization routines, instruction sections, data sections, stack sections, page tables, and interrupt and exception handling are generated by functions in the riscv_asm_program_gen class.[C3]

The article specifically focuses on riscv_asm_program_gen.sv, describing it as a class whose functions generate the complete RISC-V assembly program used to verify RISC-V IP, and noting that the class can address customization to RISC-V general-purpose registers or instructions.[C3]

Configuration and program-generation flow

The Design & Reuse article states that riscv_instr_gen_config is randomized from riscv_instr_base_test.sv. According to the article, that randomization determines the RISC-V extension, supported privilege mode, main-program and subprogram instruction counts, and whether instructions such as ebreak, dret, fence, and wfi are generated through configuration variables including no_ebreak, no_dret, no_fence, and no_wfi.[C4]

The article presents gen_program() as the main function that generates all sections of the assembly program. In the described flow, gen_program() calls functions such as get_directed_instr_stream(), add_directed_instr_stream(), gen_program_header(), gen_section("_start", str), init_gpr(), and generate_directed_instr_stream().[C5]

The same article states that generate_directed_instr_stream() inserts directed instruction streams and randomizes instruction operands such as rs1, rs2, and rd based on instruction type. It also states that riscv_instr_sequence includes generate_instr_stream, that convert2asm() is used once the instruction stream is available, and that insert_sub_program(sub_program[hart], instr_stream) is called when subprogram instructions are generated.[C5]

Tooling requirements

The README states that running the instruction generator requires an RTL simulator with SystemVerilog and UVM 1.2 support. It further states that the generator has been verified with Synopsys VCS, Cadence Incisive/Xcelium, Mentor Questa, and Aldec Riviera-PRO simulators.[C6]

Collaboration notes

The README states that RISC-V DV is now contributed to CHIPS Alliance and that regular meetings are held to discuss issues, feature priorities, and development progress. It points users to the riscv-dv-wg mail group for status, CONTRIBUTING.md for license-related questions, and the repository issue tracker for bug reports, integration issues, and feature requests.[C7]

The README also states that the project is not an officially supported Google product.[C7]

Metadata summary

These metadata values are drawn from the supplied GitHub metadata for the repository and source-file page.[C1]

References

• [C1] GitHub metadata for chipsalliance/riscv-dv and src/riscv_instr_sequence.sv.
• [C2] chipsalliance/riscv-dv README description and feature list.
• [C3] Design & Reuse article describing CHIPS Alliance development of riscv-dv and the riscv_asm_program_gen.sv class.
• [C4] Design & Reuse article section on riscv_instr_gen_config randomization.
• [C5] Design & Reuse article section on the gen_program() flow and instruction-stream generation.
• [C6] chipsalliance/riscv-dv README tooling requirements and simulator verification notes.
• [C7] chipsalliance/riscv-dv README external contributions and collaboration notes.