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Bluespec

Organization WIKI v1 · 7/4/2026

Bluespec is an organization that provides commercially available RISC-V processor designs, including the RV32I.MCU.AXI4.DM MCU core. Bluespec's RISC-V cores have been used as reference designs in verification methodologies combining Google RISCV-DV with UVM functional coverage, and in flows involving Synopsys VCS, Verdi, and the Verdi Hardware/Software Debug solution. Synopsys also publishes a Verification Reference Cookbook based on Bluespec's RV32I.MCU.AXI4.DM core.

Bluespec

Overview

Bluespec is an organization that supplies commercially available RISC-V processor designs. Evidence focuses on its role as a RISC-V core vendor whose designs have been used as the verification target in industry white papers and methodology guides.

RISC-V MCU Core

Bluespec offers a microcontroller-class RISC-V processor core identified as RV32I.MCU.AXI4.DM. This core combines the RV32I base integer instruction set with MCU-oriented features, an AXI4 interface, and a Debug Module (DM). It is referenced as a commercially available Bluespec MCU core used in verification case studies and reference methodologies.

Use in Verification Methodologies

Bluespec's RISC-V MCU core has been adopted as the example/design-under-verification (DUV) in multiple Synopsys-led RISC-V verification flows:

  • Google RISCV-DV + UVM functional coverage: A white paper on universal verification methodology coverage for RISC-V cores uses the Bluespec MCU as the target. The methodology combines RISCV-DV constrained-random instruction generation with UVM-compliant functional coverage, including merging functional coverage with code coverage and identifying coverage holes using Synopsys VCS and Verdi.
  • Synopsys Verdi Hardware/Software Debug: The Verdi HW/SW Debug solution was applied during Bluespec MCU verification to improve visibility into generated RISC-V instructions, particularly while debugging constrained-random sequences where software-side visibility is limited. The HW/SW Debug GUI synchronizes RTL-level core debugging with C/assembly-level debugging, exposing C variables, the stack, and execution state across multiple cores in an SoC.
  • Verification Reference Cookbook: Synopsys publishes a Verification Reference Cookbook for Bluespec RISC-V processors, built around the RV32I.MCU.AXI4.DM core, documenting the recommended verification methodology to use with Synopsys tools (accessed by contacting Synopsys).

Reported Advantages of the Methodology on the Bluespec Core

The Synopsys white paper highlights the following benefits demonstrated on the Bluespec MCU core:

  • Seamless integration of RISCV-DV with the readily available ISA functional coverage model, leveraging the existing RISCV-DV setup and providing a mechanism for the verification team to gauge the impact of constrained-random tests on coverage.
  • Useful during the initial phase of testbench development, when custom functional coverage is not yet defined.
  • Ability to merge functional and code coverage using Synopsys VCS and Verdi to quickly identify coverage holes.

A noted limitation is the need for two testbenches (functional and code coverage), which adds simulation and maintenance overhead; future work is expected to integrate the two into a single testbench. The methodology developed on the Bluespec core is described as readily extensible to any RISC-V processor design.

References

  • SemiEngineering: Universal Verification Methodology Coverage for Bluespec RISC-V Cores.
  • Synopsys white paper: Understanding UVM Coverage for RISC-V Processor Designs (May 2023).

CITATIONS

6 sources
6 citations
[1] Bluespec provides a commercially available RISC-V MCU core identified as RV32I.MCU.AXI4.DM. [PDF] Understanding UVM Coverage for RISC-V Processor Designs
[2] The Synopsys Verdi HW/SW Debug solution proved useful during Bluespec MCU verification by providing more visibility into generated RISC-V instructions, especially when debugging constrained-random sequences. [PDF] Understanding UVM Coverage for RISC-V Processor Designs
[3] Synopsys provides a Verification Reference Cookbook for Bluespec RISC-V processors built around Bluespec's RV32I.MCU.AXI4.DM core. [PDF] Understanding UVM Coverage for RISC-V Processor Designs
[4] A white paper explains UVM functional coverage for RISC-V cores using the Google RISCV-DV open-source project and targets Bluespec RISC-V cores. Universal Verification Methodology Coverage for Bluespec RISC-V Cores (SemiEngineering)
[5] The methodology demonstrated on the Bluespec MCU core combines RISCV-DV with a UVM-compliant functional coverage model and merges functional and code coverage using Synopsys VCS and Verdi. [PDF] Understanding UVM Coverage for RISC-V Processor Designs
[6] A limitation of the approach demonstrated on the Bluespec MCU is requiring two testbenches (functional and code coverage), with future work intended to integrate them into a single testbench. [PDF] Understanding UVM Coverage for RISC-V Processor Designs