UVM Phases

Concept

UVM phases are predefined execution points in a Universal Verification Methodology testbench. They provide a common structure for component behavior so independently developed verification components can interoperate and execute in a predictable order.

First seen 5/27/2026

Last seen 5/28/2026

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Overview

UVM phases are predefined stages in the execution of a UVM verification environment. They give verification components a shared understanding of what actions are expected at each point in the testbench flow, which helps independently developed components remain interoperable and makes testbench execution more structured and predictable.

The provided UVM phase diagram groups phases into build, run, and cleanup portions of execution. UVM components implement phase-related virtual methods according to the phases in which they participate.

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CITATIONS

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7 citations — click to expand

[1] UVM phases are predefined stages that give components shared expectations, support interoperability, and create a structured, predictable testbench execution flow. [PDF] UVM based design veri cation of a RISC-V CPU core - POLITesi

[2] The UVM phase diagram in the evidence groups execution into build, run, and cleanup phases. [PDF] UVM based design veri cation of a RISC-V CPU core - POLITesi

[3] A UVM test is the top-level object in a UVM environment, and UVM requires tests to extend uvm_test. [PDF] UVM based design veri cation of a RISC-V CPU core - POLITesi

[4] In the CV32E environment, the base test uvmt_cv32_base_test_c directly extends uvm_test, and tests should extend it to maintain the intended test flow and reduce duplicate work. [PDF] UVM based design veri cation of a RISC-V CPU core - POLITesi

[5] A typical CORE-V UVM test extends reset, configure, and run phase tasks, with reset handling reset sequencing, configure handling setup such as loading instruction memory, and run containing most procedural test code. [PDF] UVM based design veri cation of a RISC-V CPU core - POLITesi

[6] The example CORE-V run flow raises an objection, asserts fetch_en, waits for completion, and then drops the objection. [PDF] UVM based design veri cation of a RISC-V CPU core - POLITesi

[7] In the CORE-V example, programs running on the core affect the usual UVM run flow because the software execution environment is defined by the ISA, memory map, and virtual peripherals rather than by the UVM environment itself. [PDF] UVM based design veri cation of a RISC-V CPU core - POLITesi