Overview

The stuck-at-fault model is described as a common circuit-analysis technique in which a given circuit design—treated as an implementation—is modified by mutators that capture a fabrication fault model. The evidence gives an example fault model in which one or more wires connecting gates in a circuit are broken.

Testing characterization

In the cited testing methodology, stuck-at-fault testing is characterized conceptually as a white-box mutation technique. Because it is based on the implementation structure, it has the advantages and drawbacks of implementation-based testing when compared with specification-based approaches.

Effectiveness and test construction

The technique is described as very effective for medium-size circuits. It uses the structure of the given design to construct equivalence-class tests that directly incorporate a fault model.

Limitations

The evidence notes that this kind of testing technique may not reveal certain design flaws. The specific example given is a write-read error that occurs under the influence of byte alignments in memory.

Use in microprocessor test methodology

In the VAMP microprocessor case study, the authors state that although they had a VAMP gate-level model and could have applied testing at that layer, they chose instead to remain at the design level of the VAMP machine. They also note that test equivalence classes could be refined further by exploring byte-level or bit-level representations of registers and memory cells.

Relationship to conformance testing

The same source discusses test specifications that compare the final state, or part of the final state, of an execution against a system under test. This provides the surrounding testing context in which implementation-level techniques such as stuck-at-fault testing are contrasted with specification-based approaches.