Self-Consistency Universal Property
The self-consistency universal property is a design-independent formal-verification property used in processor verification. It is intended to reduce the difficulty of property formulation by allowing engineers to verify designs without writing highly design-specific specifications.[1][2]
Context
Formal verification is used to examine design behaviors thoroughly, but for large and intricate processor projects it can be complex, costly, and demanding in terms of labor and expertise.[1] In this setting, research has explored verification based on the self-consistency universal property because it is design-independent, which can reduce the burden of creating verification properties.[1][2]
Role in processor verification
The self-consistency universal property is used as a universal property for checking processor designs, rather than relying solely on manually written, design-specific properties.[1] Its appeal is that it can simplify verification for engineers by reducing the amount of design-specific property formulation required.[1]
Limitations
A single self-consistency universal property has two reported limitations:
- False positives — the property may report issues that are not actual design bugs.[1][2]
- Scalability problems — verification can suffer from exponential state-space growth.[1][2]
These limitations motivate techniques that retain the universality of the approach while improving practical effectiveness.[1]
Relationship to TIUP
The paper “TIUP: Effective Processor Verification with Tautology-Induced Universal Properties” introduces TIUP, a technique that uses tautologies as universal properties to address the limitations of the single self-consistency property.[1] TIUP treats tautologies as abstract specifications and applies them across processor data paths and control paths.[1][2]
The TIUP work was authored by Yufeng Li, Yiwei Ci, and Qiusong Yang, accepted by ASP-DAC 2024, and is available as arXiv:2404.17094.[1][2]
Summary
The self-consistency universal property is a processor-verification concept aimed at reducing the effort required to formulate formal properties by using a design-independent universal property.[1] While useful for simplifying verification, a single such property can suffer from false positives and poor scalability due to exponential state-space growth.[1] TIUP extends this line of work by using tautology-induced universal properties as abstract specifications for processor verification.[1]