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riscv_core RTL Module

CodeArtifact
First seen 6/21/2026
Last seen 6/21/2026
Evidence 1 chunks

NEIGHBORHOOD

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RELATIONSHIPS

10 connections
RISC-V implements → 97% 1e
The riscv_core RTL module is the hardware implementation of the RISC-V ISA.
XLEN uses → 98% 1e
The riscv_core RTL module is parameterized by XLEN to support 32/64/128-bit configurations.
FPU (Floating Point Unit) uses → 96% 1e
The riscv_core RTL module conditionally instantiates the FPU based on the RVF parameter.
Integer Multiply/Divide Unit uses → 95% 1e
The riscv_core RTL module conditionally instantiates the integer multiplier/divider unit based on parameters.
Parameterization uses → 97% 1e
The riscv_core RTL module is heavily parameterized to support multiple configurations.
Physical Memory Protection (PMP) implements → 88% 1e
The riscv_core RTL module implements Physical Memory Protection as part of its security features.
Privilege Modes implements → 90% 1e
The riscv_core RTL module enforces hardware privilege modes.
register bypassing implements → 88% 1e
The riscv_core RTL module implements register bypassing to mitigate data hazards.
speculative execution implements → 88% 1e
The riscv_core RTL module implements speculative execution with precise trap handling.
Non-Blocking Cache implements → 87% 1e
The riscv_core RTL module implements non-blocking caches to maximize memory bandwidth.