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Privileged CSR Randomization

Concept WIKI v1 · 5/25/2026

**Privileged CSR Randomization** is a verification feature supported by **RISCV-DV**, an open-source SystemVerilog/UVM instruction generator for RISC-V processor verification.[^ff810966] In RISCV-DV, the feature is listed as **“Privileged CSR setup randomization”**, alongside related privileged-mode verification capabilities such as privileged CSR test suites, trap/interrupt handling, page table randomization, and MMU stress testing.[^ff810966]

Privileged CSR Randomization

Privileged CSR Randomization is a verification feature supported by RISCV-DV, an open-source SystemVerilog/UVM instruction generator for RISC-V processor verification.[1] In RISCV-DV, the feature is listed as “Privileged CSR setup randomization”, alongside related privileged-mode verification capabilities such as privileged CSR test suites, trap/interrupt handling, page table randomization, and MMU stress testing.[1]

Context

RISCV-DV is designed to generate instruction streams for RISC-V processor verification and supports the RV32IMAFDC and RV64IMAFDC instruction sets.[1] It also supports multiple RISC-V privilege levels, including machine mode, supervisor mode, and user mode.[1] Within this environment, privileged CSR randomization is part of the generator’s support for testing privileged architecture behavior.[1]

Purpose

The purpose of privileged CSR randomization in RISCV-DV is to randomize the setup of privileged Control and Status Registers (CSRs) as part of verification stimulus generation.[1] This helps exercise processor behavior under varied privileged-state configurations, especially when combined with RISCV-DV’s support for privileged modes, exception generation, trap and interrupt handling, and MMU-related tests.[1]

Related RISCV-DV Features

Privileged CSR randomization is one feature in a broader RISC-V verification flow. Related RISCV-DV capabilities include:

  • Privileged mode support for machine, supervisor, and user modes.[1]
  • Page table randomization and exception generation.[1]
  • Privileged CSR test suite support.[1]
  • Trap and interrupt handling.[1]
  • MMU stress-test suite support.[1]
  • Random instruction stream generation, including branch instructions, illegal instructions, HINT instructions, sub-program generation, and random program calls.[1]
  • Directed instruction mixing, allowing hand-directed instructions to be combined with randomized instruction streams.[1]

Implementation Environment

Privileged CSR randomization is available through RISCV-DV, which is implemented as a SystemVerilog/UVM-based generator.[1] Running the generator requires an RTL simulator that supports SystemVerilog and UVM 1.2.[1] The RISCV-DV project has been verified with Synopsys VCS, Cadence Incisive/Xcelium, Mentor Questa, and Aldec Riviera-PRO simulators.[1]

Usage in Verification Flow

RISCV-DV can be used in conjunction with multiple instruction set simulators for co-simulation, including Spike, riscv-ovpsim, Whisper, and Sail RISC-V.[1] This allows generated tests involving privileged CSR setup randomization to be used as part of a broader processor verification workflow.[1]

The source code can be obtained from the RISCV-DV GitHub repository:

git clone https://github.com/google/riscv-dv.git

The project can be run either directly with Python scripts or installed as a Python package for normal use.[1]

See Also

  • RISCV-DV
  • RISC-V privileged architecture verification
  • CSR verification
  • Trap and interrupt verification
  • MMU verification

References

[1]: RISCV-DV project documentation excerpt, evidence ID ff810966-2ad0-414b-b040-4364dab496bc.