next_state macro

CodeArtifact

The `next_state` macro is an ITL architectural-style code artifact that defines the effect of an instruction, and interrupts, on a processor’s architectural state. It returns the updated architectural state, forms the core of the ISA description, and is translated into a public C++ function when generating an instruction set simulator.

First seen 5/29/2026

Last seen 5/29/2026

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WIKI

Overview

The next_state macro is an architectural-style ITL macro used to describe the state transition semantics of a processor instruction set. In the cited ISS-generation flow, an architectural-style formulation requires an explicit next_state macro that captures the effects of instructions and interrupts on the architectural state. [C1]

The macro’s return value is the architectural state after execution of the current instruction. The paper describes this as the architectural state “modified by the execution of the current instruction,” and states that next_state forms the core of the ISA. [C2]

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Next State Function implements → 100% 1e

The next_state macro implements the next state function of the ISA.

isa property ← uses 100% 1e

The isa property uses the next_state macro to capture the state transition.

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CITATIONS

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11 citations — click to expand

[1] Architectural-style formulation requires an explicit `next_state` macro that captures the effects of instructions and interrupts on architectural state. Generating an Efficient Instruction Set Simulator from a Complete Property Suite

[2] The return value of `next_state` is the architectural state modified by execution of the current instruction, and `next_state` forms the core of the ISA. Generating an Efficient Instruction Set Simulator from a Complete Property Suite

[3] The `isa` property computes `nstate = next_state(isa_state, instr)` and proves the next architectural state equals `nstate`. Generating an Efficient Instruction Set Simulator from a Complete Property Suite

[4] The architectural state is represented as a user-defined VHDL record, typically including register file, status flags, and program counter; in the example, `state` of type `state_t` holds all architectural-state elements. Generating an Efficient Instruction Set Simulator from a Complete Property Suite

[5] `instruction_t` holds decoded fields of the current instruction word, which can avoid repeated decoding in the simulator. Generating an Efficient Instruction Set Simulator from a Complete Property Suite

[6] Instruction execution in `next_state` is modeled in a case block; for an ADD opcode, the register file is updated by the sum of the source operands. Generating an Efficient Instruction Set Simulator from a Complete Property Suite

[7] The ITL `update` keyword explicitly defines write access to an array or record data structure. Generating an Efficient Instruction Set Simulator from a Complete Property Suite

[8] A reformulated architectural-style property using `next_state` captures the verified design behavior, provides a formally checkable ISA description, and is the starting point for generating a C++ ISS. Generating an Efficient Instruction Set Simulator from a Complete Property Suite

[9] ISS generation creates public functions for `next_state`, `decode`, and interface macros; the generated `Sim` class contains instruction-execution code and architectural state. Generating an Efficient Instruction Set Simulator from a Complete Property Suite

[10] The C++ generator replaces ITL/HDL data types and operations with C++ types and operations, and replaces `update` expressions with direct array or struct overwrites. Generating an Efficient Instruction Set Simulator from a Complete Property Suite

[11] Generating the ISS does not require the full RTL/ISA equivalence proof or mapping functions up front; an ITL ISA can be developed early and the ISS regenerated when the ISA changes. Generating an Efficient Instruction Set Simulator from a Complete Property Suite