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MMU Stress Testing

Concept WIKI v1 · 5/25/2026

MMU Stress Testing

Overview

MMU Stress Testing refers to verification tests that exercise memory-management-unit behavior, particularly through randomized virtual-memory/page-table scenarios and exception handling. In the RISC-V verification context, this capability is provided by RISCV-DV, an open-source SystemVerilog/UVM instruction generator for RISC-V processor verification.[1]

RISCV-DV explicitly includes a “test suite to stress test MMU” and supports related features such as page table randomization and exception generation.[1]

Role in RISC-V Processor Verification

MMU stress testing is part of a broader processor-verification flow in RISCV-DV. The generator can create randomized RISC-V instruction streams and privileged-mode scenarios that help verify processor behavior under complex memory-translation and exception conditions.[1]

RISCV-DV supports the following privileged execution modes, which are relevant to MMU and page-table behavior:

  • Machine mode
  • Supervisor mode
  • User mode[1]

Relevant RISCV-DV Capabilities

The following RISCV-DV features are directly or indirectly relevant to MMU stress testing:

Capability Relevance
Page table randomization and exception Exercises page-table setup and exception scenarios.[1]
Test suite to stress test MMU Provides dedicated MMU-focused stress testing.[1]
Privileged CSR setup randomization Randomizes privileged control/status-register configuration used in privileged execution tests.[1]
Privileged CSR test suite Tests privileged CSR behavior that may interact with memory-management and privilege mechanisms.[1]
Trap/interrupt handling Supports verification of trap and interrupt flows, including exception-related behavior.[1]
Co-simulation with multiple ISS Allows comparison against instruction-set simulators including Spike, riscv-ovpsim, Whisper, and Sail-RISC-V.[1]

Supported RISC-V Targets

RISCV-DV supports the following instruction-set configurations:

  • RV32IMAFDC
  • RV64IMAFDC[1]

These supported configurations allow MMU-related stress tests to be generated for both 32-bit and 64-bit RISC-V targets within the listed ISA feature sets.[1]

Tool and Environment Requirements

To run RISCV-DV, an RTL simulator with SystemVerilog and UVM 1.2 support is required.[1]

The generator has been verified with the following simulators:

  • Synopsys VCS
  • Cadence Incisive/Xcelium
  • Mentor Questa
  • Aldec Riviera-PRO[1]

The EDA tool environment should be properly configured before running the generator.[1]

Getting RISCV-DV

The RISCV-DV source can be obtained from GitHub:

git clone https://github.com/google/riscv-dv.git

[1]

Running RISCV-DV

RISCV-DV can be run directly through Python scripts, which is recommended for developers working with multiple clones:

pip3 install -r requirements.txt
python3 run.py --help

[1]

For normal users, RISCV-DV can also be installed as a Python package in editable user mode:

export PATH=$HOME/.local/bin/:$PATH
pip3 install --user -e .

This allows repository changes to become immediately available when using the run or cov commands.[1]

Verification Integration

RISCV-DV supports co-simulation with multiple instruction-set simulators:

  • Spike
  • riscv-ovpsim
  • Whisper
  • Sail-RISC-V[1]

This co-simulation support can be used as part of a verification flow to compare generated-test behavior across implementations or reference models.[1]

Related Generator Features

In addition to MMU-focused stress testing, RISCV-DV includes several randomized and directed-test capabilities that can be combined with MMU scenarios:

  • Sub-program generation and random program calls
  • Illegal instruction and HINT instruction generation
  • Random forward and backward branch instructions
  • Mixing directed instructions with random instruction streams
  • Debug mode support with a randomized debug ROM
  • Instruction-generation coverage model
  • Handshake communication with the testbench
  • Support for hand-coded assembly tests[1]

Documentation and Community

RISCV-DV documentation is available under the repository’s docs directory, and a prebuilt HTML document is available under docs/build/singlehtml/index.html.[1]

RISCV-DV has been contributed to CHIPS Alliance, and the project has regular meetings to discuss issues, feature priorities, and development progress.[1] The project also provides a mailing group for current status and accepts bug reports, integration issues, and feature requests through its repository issue tracker.[1]

See Also