Micro-Architecture Verification
ConceptMicro-architecture verification is a part of CPU verification that focuses on the processor's internal logical building blocks—such as the fetch, execution, load/store units, and caches—rather than only its externally visible instruction-set behavior. In RISC-V contexts, the openness of the ISA amplifies verification complexity because users may add custom instructions and micro-architectural features, each of which roughly doubles verification effort, and modern practice typically combines constrained-random simulation, formal property checking, and hardware-assisted techniques such as emulation.
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Definition
Micro-architecture verification is the CPU verification activity that checks the functional correctness of a processor's internal logical building blocks—such as the fetch unit, execution unit, load/store unit, and cache—rather than only its externally visible instruction-set behavior. It is typically carried out as an IP- or block-level verification plan that sits between architectural compliance and full-chip integration within a broader CPU verification effort.
Role in CPU verification
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2 connectionsMicro-architecture verification is a key part of overall processor verification.
Pipeline verification is a key aspect of micro-architecture verification.
CITATIONS
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[1] Micro-architecture verification is the second of at least three CPU verification planning areas (alongside architecture verification and performance verification), organized as multiple sub-test plans for logical building blocks such as the fetch unit, execution unit, load/store unit, and cache. UVM based design verification of a RISC-V CPU core (POLITesi)
[2] A micro-architecture verification plan should capture both 'what to verify' and 'how to verify,' including stimulus infrastructure, randomization knobs, sequences and tests, coverage properties, checking mechanisms, and a testbench block diagram. UVM based design verification of a RISC-V CPU core (POLITesi)
[3] Checking mechanisms are implemented as scoreboards, interface assertions, and embedded assertions inside RTL or verification components; constrained-random/coverage-driven simulation is the common strategy, with formal or other techniques used selectively. UVM based design verification of a RISC-V CPU core (POLITesi)
[4] Modern verification uses object-oriented programming concepts for efficiency and reusability, and SystemVerilog is identified as the language of choice for verification tasks. UVM based design verification of a RISC-V CPU core (POLITesi)
[5] Typical processor sub-units targeted by micro-architectural verification include branch prediction, parts of a pipeline, memory systems (e.g. caches), prefetch buffer, ALUs, register models, multipliers, and the load/store unit. RISC-V Micro-Architectural Verification (Semiconductor Engineering)
[6] A property- and command-based sub-unit verification flow uses a generator that builds command sequences, keeps extending them until a sequence breaks with respect to a golden reference model, and then shrinks the sequence by removing commands that do not affect the bug—helping with diagnosis, debugging, and fixing. RISC-V Micro-Architectural Verification (Semiconductor Engineering)
[7] Micro-architectural verification happens in two ways: architectural verification assertions and covers fail in formal (picking up RTL-induced architectural, safety, or security (CIA) violations); and checks/covers are showered across RTL interfaces so formal tools pick up failures across components, improving bug hunting, compositional proof convergence, and overall coverage. RISC-V Micro-Architectural Verification (Semiconductor Engineering)
[8] Control paths are challenging to verify with simulation, and data paths are at a scale where simulation cannot be exhaustive, so properties are written and verified with formal; constrained-random can give good coverage but risks leaving corner cases that formal would catch. RISC-V Micro-Architectural Verification (Semiconductor Engineering)
[9] Comparing an implementation against a golden model by instruction traces has real issues with asynchronous events, multi-issue pipelines, and out-of-order execution; the ISA does not specify every aspect (e.g. which of six same-priority interrupts is taken and at which pipeline stage), so micro-architectural choices vary from core to core. RISC-V Micro-Architectural Verification (Semiconductor Engineering)
[10] To avoid desynchronization between a golden reference model and a DUT caused by timer interrupts, a timer interrupt can be issued every 5,000 retired instructions instead of every 1 million clock cycles; if the DUT and golden model are good, the same number of instructions is executed with the timer removed. RISC-V Micro-Architectural Verification (Semiconductor Engineering)
[11] RISC-V's flexibility and extensibility, together with new extensions (e.g. vector) and user-defined custom instructions, make verification hard; every addition roughly doubles verification and complexity, requiring full re-verification of the design, including pipeline, ALU conflicts, caching system, and load/store interactions. RISC-V Micro-Architectural Verification (Semiconductor Engineering)
[12] RISC-V implementations are beginning to include speculative execution, with out-of-order execution coming; these techniques raise security concerns such as Spectre and Meltdown, which must be considered in verification. RISC-V Micro-Architectural Verification (Semiconductor Engineering)
[13] Coverage tells you that you have done something and gives a level of confidence, but does not guarantee the absence of problems; with modern processor complexity, coverage alone is not sufficient. RISC-V Micro-Architectural Verification (Semiconductor Engineering)
[14] Processor coverage is unique: touching every one of the 432 million instruction variants only tests the decoder, not sequences, combinations, or pipeline behavior; better practice is to focus on the combinations of instructions that designers are most worried about rather than generating billions of random instructions. RISC-V Micro-Architectural Verification (Semiconductor Engineering)
[15] After sub-units are verified, integration uses a mixed strategy: formal (exercising every possible input combination to break ISA-specified behavior captured as SystemVerilog assertions), UVM testbenches and test software, and emulation for large processors and SoC integration. RISC-V Micro-Architectural Verification (Semiconductor Engineering)
[16] Hardware-assisted verification—virtual prototype capabilities, emulation, and hardware prototyping—is critical for understanding how micro-architectural decisions affect the full SoC and the workloads running on it, especially with new custom instructions and items such as vector extensions. RISC-V Micro-Architectural Verification (Semiconductor Engineering)
[17] Booting Linux is itself a powerful verification step: surprisingly many bugs can be present in a core while still booting Linux, and bugs found this way (asynchronous effects, timers, timing-base differences between simulation and FPGA-based emulation) often do not show up in any other kind of verification. RISC-V Micro-Architectural Verification (Semiconductor Engineering)