Instruction-Level Unit Testing

Concept

Based on the cited TestRIG paper, instruction-level unit testing refers here to testing CPUs with short injected instruction sequences and then minimizing failing cases with shrinking. The evidence specifically supports smart shrinking, non-shrinkable initialization sequences, and embedded assertions as key techniques for isolating interesting instruction-level failures.

First seen 6/2/2026

Last seen 6/2/2026

Evidence 3 chunks

Wiki v1

WIKI

Overview

In the cited TestRIG work on randomized testing of RISC-V CPUs using direct instruction injection, instruction-level unit testing is represented by executing instruction sequences directly against an implementation and then analyzing counterexamples at instruction granularity. The paper emphasizes reducing failing sequences to small, interpretable tests rather than keeping long randomized traces.^[1]

Core techniques supported by the evidence

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RELATIONSHIPS

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TestRIG compares with → 100% 2e

TestRIG is compared favorably against instruction-level unit testing, eventually replacing it.

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CITATIONS

7 sources

7 citations — click to expand

[1] Smart shrinking removes and transforms instructions to minimize failing sequences. Randomized Testing of RISC-V CPUs using Direct

[2] Smart shrinking can propagate an instruction's output register to future operands, enabling additional reduction of a counterexample. Randomized Testing of RISC-V CPUs using Direct

[3] Non-shrinkable sequences preserve required initialization during shrinking. Randomized Testing of RISC-V CPUs using Direct

[4] A non-shrinkable initialization sequence helped move past trivial counterexamples caused by uninitialized floating-point registers to more interesting divergences in exception conditions and rounding modes. Randomized Testing of RISC-V CPUs using Direct

[5] Assertions allow failures without divergence and without tandem verification. Randomized Testing of RISC-V CPUs using Direct

[6] The paper uses assertions in instruction sequences to test the limits of implementation-defined behavior. Randomized Testing of RISC-V CPUs using Direct

[7] TestRIG QCVEngine is the implementation context discussed in the evidence. Randomized Testing of RISC-V CPUs using Direct