instrADD property

CodeArtifact

The `instrADD` property is an ITL operation property for an ADD instruction in a processor property suite. It decodes fields from the instruction word, assumes the processor is ready to execute an ADD, and proves that the destination register is updated with the sum of two source registers via the `write_reg` macro.

First seen 5/29/2026

Last seen 5/29/2026

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Overview

instrADD is shown as an operation property in the paper Generating an Efficient Instruction Set Simulator from a Complete Property Suite. It specifies the behavior of an ADD instruction in ITL as part of a property-suite-based processor model. In the complete-property-suite approach described by the paper, successfully verified properties can form a model of the verified design by uniquely describing transitions and output behavior; this model can then be exploited to generate an executable simulator. [C1]

Structure

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RELATIONSHIPS

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write_reg macro uses → 100% 1e

The instrADD property uses the write_reg macro to express register file updates.

Complete Property Suite part of → 95% 1e

The instrADD property is one property in the complete property suite describing ADD instruction behavior.

LINKED ENTITIES

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write_reg macro USES Extracted graph relationship

Complete Property Suite PART_OF Extracted graph relationship

CITATIONS

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[1] A successfully verified complete property suite can form a model of the verified design by uniquely describing transitions and output behavior, and can be exploited to obtain an executable simulator. Generating an Efficient Instruction Set Simulator from a Complete Property Suite

[2] `instrADD` is shown as an operation property with `freeze`, `assume`, and `prove` sections that decode instruction fields, assume ADD execution readiness, and prove a `write_reg` update. Generating an Efficient Instruction Set Simulator from a Complete Property Suite

[3] The paper explains that the `freeze` section decomposes the instruction word into opcode and register addresses; the `assume` part states that an ADD instruction is ready to execute; and the proof shows that one time step later the register file is updated with the correct value. Generating an Efficient Instruction Set Simulator from a Complete Property Suite

[4] The `write_reg` macro iterates over registers `0..7`, updates the selected register with `res(15 downto 0)`, and leaves non-selected registers unchanged. Generating an Efficient Instruction Set Simulator from a Complete Property Suite