Dynamic Binary Translation (DBT)

Concept

Dynamic Binary Translation (DBT) is identified in the provided evidence as the execution technique used by QEMU, an open-source machine emulator. In QEMU, DBT is associated with a modular translation pipeline that uses the architecture-agnostic Tiny Code Generator (TCG) intermediate representation to connect guest instruction frontends with host backends.

First seen 5/29/2026

Last seen 5/29/2026

Evidence 1 chunks

Wiki v1

WIKI

Overview

Dynamic Binary Translation (DBT) is described in the provided evidence as a technique used by QEMU, an open-source machine emulator. The evidence presents QEMU as using DBT within a modular architecture that simplifies support for new architectures, employs an architecture-agnostic intermediate representation called TCG, and includes reusable infrastructure such as a GDB stub.

Role in QEMU

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NEIGHBORHOOD

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RELATIONSHIPS

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QEMU ← implements 100% 1e

QEMU implements dynamic binary translation as its core emulation technique.

LINKED ENTITIES

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QEMU IMPLEMENTS Extracted graph relationship

CITATIONS

5 sources

5 citations — click to expand

[1] QEMU is an open-source machine emulator that uses dynamic binary translation (DBT). Generation of a QEMU-Based Instruction Set Simulator from a Processor Description in OpenVADL

[2] QEMU's modular architecture uses an architecture-agnostic IR called TCG and includes reusable infrastructure such as a GDB stub. Generation of a QEMU-Based Instruction Set Simulator from a Processor Description in OpenVADL

[3] The evidence illustrates QEMU translation from a RISC-V frontend through TCG IR to an x86_64 backend. Generation of a QEMU-Based Instruction Set Simulator from a Processor Description in OpenVADL

[4] OpenVADL generates QEMU frontends by lowering VIAM to TCG operations and generating C code. Generation of a QEMU-Based Instruction Set Simulator from a Processor Description in OpenVADL

[5] The OpenVADL slides report evaluation on RISC-V 64 and AArch64 Embench workloads and conclude that the generated frontend achieves up to 44% lower runtime than upstream. Generation of a QEMU-Based Instruction Set Simulator from a Processor Description in OpenVADL