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Domain Specific Language (DSL) for ISA Description

Concept WIKI v1 · 6/7/2026

A Domain Specific Language (DSL) for ISA description is a specialized formalism used to give a functional description of an Instruction Set Architecture. In the RISC-V verification context, such a DSL is envisioned as a machine-readable source from which instruction set constraints can be extracted and fed into constrained-random test generation flows. CoreDSL is a representative tool that implements this idea.

Overview

A Domain Specific Language (DSL) for ISA description is a purpose-built, machine-readable formalism that captures the functional semantics of a processor's Instruction Set Architecture (ISA). Rather than relying on ad hoc prose or hand-written templates, a DSL encodes the ISA in a structured way so that downstream tools can reason about instruction encodings, operands, legal/illegal states, and the architectural behavior of individual instructions.

Role in Constrained Random Verification

In Constrained Random Verification (CRV) flows for RISC-V, the proposed use of a DSL for ISA description is to serve as the authoritative source of instruction-set constraints that drive random test generation. By parsing a single, formal ISA description, a test-generation framework can:

  • Extract per-instruction operand domains, formats, and legality conditions.
  • Build SystemVerilog/UVM constraint models that mirror the ISA semantics.
  • Keep the test generator automatically in sync with ISA updates, since the constraints are derived directly from the formal description rather than maintained by hand.

This idea is proposed in the context of the RISC-V DV framework, where the authors envision extending the existing CRV infrastructure by deriving constraints from a DSL instead of encoding them manually.

CoreDSL as an Implementation

CoreDSL is identified as an example of a DSL for functional RISC-V ISA description. It instantiates the concept of a DSL-driven ISA model: the language itself is the artifact, and a front-end/tool chain is expected to translate it into the constraints and metadata needed by a constrained-random testbench.

Envisioned Benefits

Using a DSL as the root of the test-generation pipeline is motivated by several factors discussed in the CRV-for-RISC-V literature:

  • Single source of truth for ISA semantics, removing duplication between the reference model, the testbench constraints, and documentation.
  • Reusability across different verification environments (ISS, RTL, virtual prototypes, formal frameworks).
  • Extensibility for RISC-V extensions, since a new extension can be added by writing a new module in the DSL rather than rewriting constraints in multiple places.

Status in the Literature

The use of a DSL for ISA description to drive CRV is presented in the referenced work as a future work / envisioned direction rather than a fully realized feature. The authors explicitly note that they "envision to extract instruction set constraints for the purpose of test generation from a Domain Specific Language (DSL) for functional RISC-V ISA description (such as the CoreDSL)." This frames the DSL-based approach as an integration target for existing RISC-V DV, ISS-based, and UVM-based verification methodologies.

Related Concepts

  • Constrained Random Verification (CRV) – the verification methodology that the DSL is meant to feed.
  • ISS (Instruction Set Simulator) – provides architectural state that, in combination with DSL-derived constraints, can guide on-the-fly test generation.
  • CoreDSL – a concrete tool that implements the DSL-for-ISA-description concept.

LINKED ENTITIES

1 links
CoreDSL IMPLEMENTS

CITATIONS

2 sources
2 citations
[1] A Domain Specific Language (DSL) for functional RISC-V ISA description can be used to extract instruction set constraints for the purpose of test generation, with CoreDSL given as an example implementation. Constrained Random Verification for RISC-V: Overview, Evaluation and Discussion
[2] Extracting constraints from a DSL for ISA description is presented as an envisioned future-work extension to the RISC-V DV constrained-random verification flow, intended to be interleaved with existing test-generation methods. Constrained Random Verification for RISC-V: Overview, Evaluation and Discussion