congestor

Concept

A congestor is the simplest Logic Fuzzer mechanism described by Kabylkas et al. for processor verification. It is inserted on signals such as FIFO full, busy, ready, or ready-valid handshake signals and is randomly activated to create artificial backpressure, thereby stirring execution and exposing additional design behavior during simulation.

First seen 5/27/2026

Last seen 5/27/2026

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Wiki v1

WIKI

Definition

A congestor is described as the simplest type of Logic Fuzzer. It is an inserted hardware-fuzzing mechanism that artificially asserts a congestion-related signal, such as a FIFO full signal, even when the design condition for that signal has not actually been met. When randomly activated, the congestor creates artificial backpressure in the design. [C1]

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Logic Fuzzer ← uses 100% 2e

Logic Fuzzer implements congestors as one of its fuzzing mechanisms.

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CITATIONS

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[1] A congestor is the simplest type of Logic Fuzzer and can artificially assert a FIFO full signal to create backpressure. [PDF] Effective Processor Verification with Logic Fuzzer Enhanced Co ...

[2] Verification engineers identify congestible points, configure the fuzzer to create matching congestor objects, and set each congestor’s period and random seeds in JSON. [PDF] Effective Processor Verification with Logic Fuzzer Enhanced Co ...

[3] Congestors are evaluated by rerunning tests after insertion and observing new design activity, with toggle coverage used as a proxy metric. [PDF] Effective Processor Verification with Logic Fuzzer Enhanced Co ...

[4] In BOOM, a congestor on the ROB ready signal caused 12 additional frontend signals, 40 core signals, and 32 load-store-unit signals to toggle, activating logic not touched by more than 200 tests. [PDF] Effective Processor Verification with Logic Fuzzer Enhanced Co ...

[5] A proof-of-concept BOOM flow automatically inserted congestors by annotating Chisel RTL signals and using Chiffre/FIRRTL to instrument the design. [PDF] Effective Processor Verification with Logic Fuzzer Enhanced Co ...

[6] Logic Fuzzer may create unreachable microarchitectural states, but co-simulation failures exposed by fuzzing are treated as potential bugs to prove or disprove. [PDF] Effective Processor Verification with Logic Fuzzer Enhanced Co ...