Overview
The Command and Data Instruction Level is a level of abstraction used in stimulus (test) generation for hardware design verification. In this level, the stimuli directed at the Design Under Verification (DUV) are described as groups of instructions — each instruction carrying an operation (command) along with the associated data — rather than as raw bit patterns or as high-level scenario sequences.
It is one of three commonly distinguished levels used in constrained-random and directed stimulus generation:
- Sequence Level — the highest level; stimuli are described as groups of instructions at the scenario/transaction level.
- Command and Data Instruction Level — an intermediate level; stimuli are expressed as discrete commands and their associated data items.
- Bit Level — the lowest level (no abstraction); stimuli are described as raw groups of bits driven onto the DUV.
In the typical abstraction diagram, the Sequence Level sits on top of the Command and Data Instruction Level, which in turn sits on top of the Bit Level, with the DUV receiving the resulting stimuli.
What "Abstraction Level" Means Here
When choosing an abstraction level for stimuli generation, three communication channels are considered:
- Communication between the user (verification engineer) and the generator — defines how directives are specified to the generator.
- Internal representation and operation level in the generator — defines the level at which the generator internally builds the stimuli.
- Communication between the generator and the driver — the generator may emit high-level items and the driver translates them into bits using the appropriate bus/protocol.
These three channels need not share the same level, and the Command and Data Instruction Level can be chosen for one or more of them.
Choosing the Command and Data Instruction Level
- For user ↔ generator interaction, the recommendation is to use a level similar to that used in the verification plan — which in the running example presented in the source material is the sequence level rather than the command/instruction level.
- For the internal representation of the generator, the source notes conflicting requirements: user-facing concerns favor a high level of abstraction, while detailed stimulus construction favors a low level of abstraction. In practice, generators often use two or more levels: first building a high-level skeleton of stimuli from user requirements, then adding lower-level details.
- For generator ↔ driver interaction, the general rule is to use the lowest level at which the generator operates; this can make the Command and Data Instruction Level the natural unit exchanged with the driver, with the driver translating the command/data into bit-level protocol signaling.
Trade-offs vs. the Bit Level
Working at the Command and Data Instruction Level hides the bit-level details from most of the generator logic, which keeps stimulus code readable and aligned with how verification engineers think about operations. However, certain tasks — most notably error injection — are usually done at the lowest (bit) level of abstraction: the value of a bit or set of bits is flipped when injected into the DUV. To allow error injection, the generator must be able to operate and communicate with the driver at the bit level, which adds burden and complexity for the normal (non-error) cases that do not require that fidelity.
Where It Fits
The Command and Data Instruction Level is part of the broader Level of Abstraction taxonomy applied to verification stimuli. It is the natural choice when the verification plan refers to commands and data rather than full sequences or bit patterns, and when the generator needs a more concrete representation than sequences but should still be insulated from protocol-level bit details.