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Coherence of Read-Read (CoRR)

Concept WIKI v1 · 7/3/2026

Coherence of Read-Read (CoRR) is a memory consistency axiom that requires each load to return the value of the most recent store to the same address in both program order and the Global Memory Order (GMO). A violation of CoRR manifests as memory appearing to "go backward in time," where a younger load returns a value older than a previous load from the same address.

Coherence of Read-Read (CoRR)

Definition

Coherence of Read-Read (CoRR) is a memory consistency axiom that constrains the behavior of multiple loads from the same address by a single hart. It mandates that each load must return the value of the most recent store to that address that precedes it in both program order and the Global Memory Order (GMO) [1]. This is part of the broader load value axiom framework that underpins the memory consistency model.

Relation to RVWMO

CoRR is an instance of the more general coherence requirements that fall under the RISC-V Weak Memory Ordering (RVWMO) model. It applies to single-hart execution: a hart must not observe memory that "goes backward in time" with respect to loads to the same address.

What Constitutes a Violation

A violation of CoRR occurs when:

  • A younger load (e.g., x3) observes an older value than an earlier load (e.g., x2) from the same address.
  • This breaks the Preserved Program Order (PPO) ordering between the two loads.
  • The result is that memory appears to "go backward in time," with a later load returning a value that is older (in store order) than the value previously read by an earlier load.

Example Scenario

Consider a hart executing two loads from the same address after intervening writes:

  1. Load x2 reads value V2.
  2. Load x3 reads value V1, where V1 is older than V2 in the GMO.

This outcome constitutes a CoRR violation because load x3 does not return the value of the most recent store preceding it in both program order and the GMO.

Detection via Fuzzing

The HARTBREAKER framework [1] demonstrates how CoRR violations can be detected in multi-hart RISC-V CPUs through deterministic fuzzing. The fuzzer generates programs with multiple loads of different widths (e.g., lb, lbu, lwu) from the same address, interleaved with stores, and uses memory consistency solvers to check for forbidden outcomes.

Related Concepts

  • RVWMO: The RISC-V Weak Memory Ordering model under which CoRR is defined.
  • Load Value Axiom: The broader principle requiring loads to return the most recent store value in both program order and GMO.
  • Preserved Program Order (PPO): The ordering between memory operations that must be maintained; CoRR violations indicate PPO is not preserved between same-address loads.

LINKED ENTITIES

1 links
RVWMO PART_OF

CITATIONS

3 sources
3 citations
[1] CoRR mandates that each load returns the value of the most recent store that precedes it in both program order and the GMO HARTBREAKER: Deterministic Fuzzing of Multi-Hart RISC-V CPUs
[2] A CoRR violation occurs when a younger load observes an older value than an earlier load from the same address, breaking PPO ordering HARTBREAKER: Deterministic Fuzzing of Multi-Hart RISC-V CPUs
[3] CoRR violation means the hart observes memory that goes backward in time, i.e., a younger load returns a value older than a previous load from the same address HARTBREAKER: Deterministic Fuzzing of Multi-Hart RISC-V CPUs