Overview

cip_lib is a SystemVerilog verification library used within the OpenTitan project. It provides shared verification infrastructure intended to be reused across the design verification (DV) testbenches of Comportable IPs.

Beyond general DV utilities, cip_lib includes specific support for security countermeasure verification.

Security Verification in cip_lib

cip_lib plays a role in the verification of security countermeasures implemented in OpenTitan design blocks:

• Common security countermeasures (such as shadowed registers, hardened counters, and other primitives) can be fully verified or partially handled by cip_lib.
• Verification engineers are expected to follow the dedicated cip_lib documentation to enable the common countermeasure testpoints.
• Where applicable, common security countermeasure tests and testplans should be imported into a DUT's testplan to cover the auto-generated security countermeasure testpoints produced by the reggen tool.

The behavioral assertions used to verify these common countermeasures in simulation are documented under the Security Countermeasure Verification Framework, and the corresponding formal property verification (FPV) testbench setup is described in the formal verification documentation for common countermeasure primitives.

Use in DV Signoff

The OpenTitan DV signoff checklist treats cip_lib as a standard resource for verifying common security countermeasures at the V2 to V3 transition:

• The DUT's testplan should be updated with the necessary testpoints and covergroups to verify all implemented security countermeasures, using the auto-generated _sec_cm_testplan.hjson produced by reggen.
• Tests mapped to these testpoints should leverage cip_lib where the countermeasures are common across IPs.
• The security countermeasure testplan and overall DV effort are reviewed by stakeholders such as the DUT designer(s), peer DV engineer(s), and the security architect.

See the references below for the authoritative documentation.