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CGF Format

Concept WIKI v1 · 7/3/2026

The CGF (Coverage Group Format) is the coverpoint specification language used by RISCV-ISAC to express architectural coverage goals. It allows coverpoints to be written as pure Python expressions over instruction fields and is consumed by RISCV-CTG to drive Constraint Satisfaction Problem (CSP) solving for test generation.

CGF Format

Overview

The CGF (Coverage Group Format) is the coverpoint specification format defined and used by RISCV-ISAC. A coverpoint in CGF specifies a boolean expression over the fields of an architectural element (instruction or architectural state) that must be covered during execution of a test [1].

Unlike classical Design Verification (DV) approaches where coverpoints are defined in SystemVerilog/UVM against the RTL — which carries a high entry barrier and makes it extremely difficult to cover all architectural options in a single RTL — ISAC expresses coverpoints as pure Python expressions [1].

Structure of a CGF Covergroup

A CGF file is organized into covergroups. The following example illustrates the structure for an add instruction [1]:

add_cov:
    config: [check ISA:= regex(.*I.*)]
    opcode: {add: 0}
    rs1: {x1: 0, x3: 0}
    rs2: {x2: 0, x4: 0}
    op_comb: {'rs1 == rs2 != rd': 0}
    val_comb:
        'rs1_val > 0 and rs2_val > 0': 0
        'rs1_val > 0 and rs2_val < 0': 0
        abstract_comb:
        'walking_ones("rs1_val", 64)': 0
        'walking_zeros("rs1_val", 64)': 0
    csr_comb: {'mtval == 0xdeadbeef': 0}
    cross_coverage:
        # <> implies a list, ? implies don't care
        # <inst-opcode> :: <var-assign> :: <val-rules>
        '[(add) : (sw)] :: [a=rd : ?] :: [? : rs2==a or rs1==a]': 0

Coverpoint Categories

Coverpoints in CGF are categorized based on the variables/fields that can be tested [1]:

  • Instruction Mnemonics (Opcode) — the operation covered.
  • Register Operands — specific architectural registers (e.g., rs1, rs2).
  • Operand Combinations (op_comb) — relationships between operands.
  • Value Combinations (val_comb) — relationships and constraints on operand values.
  • CSR Value Combinations (csr_comb) — constraints on Control and Status Register values.
  • Cross Combinations (cross_coverage) — coverage across multiple instructions, using the convention:
    • <inst-opcode> :: <var-assign> :: <val-rules>
    • <> implies a list
    • ? implies don't care

Abstract Combinations

CGF supports custom functions written in Python (abstract_comb), which are resolved into the standard coverpoints during normalization [1].

Configuration Guards

A config entry allows an ISA regex guard to scope a covergroup, e.g., check ISA:= regex(.*I.*) restricts the covergroup to the I extension [1].

Usage in the RISC-V Test Toolchain

RISCV-ISAC

ISAC parses CGF files to evaluate coverage from an instruction trace generated by the implementation/model. The trace contains instruction address, instruction encoding, and architectural state changes (CSR and register file updates) [2].

RISCV-CTG

RISCV-CTG consumes CGF coverpoints to generate tests. For each instruction, CTG maintains an internal database containing relevant fields and their domains, and uses the CGF format defined by ISAC to generate tests from coverpoints [2].

The coverpoints are modeled as a classical Constraint Satisfaction Problem (CSP) [2]:

  • A CSP solver (e.g., python-constraint) is employed to find solutions.
  • op_comb and val_comb coverpoints are solved independently.
  • Two solver types are supported:
    • Min-Conflict
    • Backtracking
  • The solver may be skipped for coverpoints suffixed with #nosat (useful when a coverpoint fully defines all instruction fields, e.g., rs1_val == 2 and rs2_val == 5) [2].

Once solutions are found, CTG interleaves op_comb and val_comb solutions, fills in additional fields such as the signature pointer register, filters out test cases that fail to hit at least one unique coverpoint, and substitutes values into assembly macro templates to emit assembly files [2].

Role in the Specification

The CGF format is the concrete expression of the broader ISA Coverage Specification, serving as the structured, machine-readable definition of coverpoints that both ISAC and CTG operate on.

CITATIONS

8 sources
8 citations
[1] A coverpoint specifies a boolean expression over the fields of an architectural element (instruction/state) that is required to be covered during execution. Automating Generation and Maintenance of a High-Quality Architectural Test Suite for RISC-V - CARRV at ISCA 2022
[2] In ISAC, coverpoints are expressed as pure Python expressions, in contrast to classical DV coverpoints in SV-UVM. Automating Generation and Maintenance of a High-Quality Architectural Test Suite for RISC-V - CARRV at ISCA 2022
[3] CGF coverpoints are categorized by instruction mnemonics (opcode), register operands, operand combinations, value combinations, CSR value combinations, and cross combinations. Automating Generation and Maintenance of a High-Quality Architectural Test Suite for RISC-V - CARRV at ISCA 2022
[4] Custom Python functions (abstract_comb) are resolved into standard coverpoints during normalization. Automating Generation and Maintenance of a High-Quality Architectural Test Suite for RISC-V - CARRV at ISCA 2022
[5] RISCV-CTG uses the CGF format defined by ISAC and models coverpoints as a Constraint Satisfaction Problem, solved independently for op_comb and val_comb using Min-Conflict or Backtracking solvers. Automating Generation and Maintenance of a High-Quality Architectural Test Suite for RISC-V - CARRV at ISCA 2022
[6] A #nosat suffix can be used on a coverpoint to skip the CSP solver when all instruction fields are fully defined. Automating Generation and Maintenance of a High-Quality Architectural Test Suite for RISC-V - CARRV at ISCA 2022
[7] CTG interleaves op_comb and val_comb solutions, filters test cases so that each hits at least one unique coverpoint, and substitutes values into assembly macro templates to emit assembly files. Automating Generation and Maintenance of a High-Quality Architectural Test Suite for RISC-V - CARRV at ISCA 2022
[8] ISAC evaluates coverage from an instruction trace containing instruction address, instruction encoding, and architectural state changes (CSR and register file updates). Automating Generation and Maintenance of a High-Quality Architectural Test Suite for RISC-V - CARRV at ISCA 2022